UJA1065TW/5V0,518 NXP Semiconductors, UJA1065TW/5V0,518 Datasheet - Page 32
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UJA1065TW/5V0,518
Manufacturer Part Number
UJA1065TW/5V0,518
Description
IC CAN/LIN FAIL-SAFE 32HTSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1065TW3V3CT.pdf
(76 pages)
Specifications of UJA1065TW/5V0,518
Package / Case
32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
Applications
Networking
Interface
CAN, LIN
Voltage - Supply
5.5 V ~ 52 V
Mounting Type
Surface Mount
Product
Controller Area Network (CAN)
Number Of Transceivers
1
Data Rate
20 Kbps
Supply Voltage (max)
27 V, 52 V
Supply Voltage (min)
5.5 V
Supply Current (max)
10 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4374-2
935281292518
UJA1065TW/5V0-T
UJA1065TW/5V0-T
935281292518
UJA1065TW/5V0-T
UJA1065TW/5V0-T
NXP Semiconductors
Table 6.
[1]
[2]
[3]
Table 7.
UJA1065_7
Product data sheet
Bit
11 to 6
Bit
15 and 14
13
12
The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f
See
The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is
immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry
without dips on V1; see
Section
Mode register bit description (bits 11 to 6)
System Status register bit description
Symbol
NWP[5:0]
Symbol
A1, A0
RRS
RO
6.13.4 System Status register
6.4.4.
This register allows status information to be read back from the SBC. This register can be
read in all modes.
Section
Description
Nominal
Watchdog Period
WDPRE = 11 (as
set in the Special
Mode register)
Description
register address
Read Register Select
Read Only
6.4.4.
Value
00 1001
00 1100
01 0010
01 0100
01 1011
10 0100
10 1101
11 0011
11 0101
11 0110
Rev. 07 — 25 February 2010
Value
00
0
0
1
[1]
…continued
Time
Normal
mode (ms)
14
28
56
112
140
168
196
244
252
280
Function
read System Status register
read System Status register without writing to Mode
register
read System Status register and write to Mode register
High-speed CAN/LIN fail-safe system basis chip
Standby
mode (ms)
70
140
280
560
1120
2240
3584
7168
14336
OFF
[2]
Flash mode
(ms)
70
140
280
560
1120
2240
3584
7168
14336
28672
UJA1065
osc
© NXP B.V. 2010. All rights reserved.
= 512 kHz.
Sleep mode
(ms)
560
1120
2240
3584
7168
10752
14336
21504
28672
OFF
[3]
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