ISD-300A1 Cypress Semiconductor Corp, ISD-300A1 Datasheet - Page 17

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ISD-300A1

Manufacturer Part Number
ISD-300A1
Description
IC USB 2.0 BRIDGE BULK 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of ISD-300A1

Applications
USB 2.0 to ATA/ATAPI Bridge
Interface
ATA, ATAPI
Voltage - Supply
3 V ~ 3.6 V
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1459

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISD-300A1
Manufacturer:
CYP
Quantity:
20 000
Company:
Part Number:
ISD-300A1
Quantity:
963
October 19, 2001
Address
0xB
ATA Data Setup
Drive Power Valid
Polarity
Override PIO Timing
Drive Power Valid
Enable
ATA Read Kludge
I_MODE
Field Name
Bits (7:5)
Setup time is only incurred on the first data cycle of a burst. Standard values
for ATA compliant devices and a 30.0 MHz system clock are (in binary):
Note: These values are only valid when the Override PIO Timing
configuration bit is set.
mode 0
mode 1
mode 2
mode 3
mode 4
Bit (4)
Controls the polarity of DRV_PWR_VALID pin
0
1
Bit (3)
This field is used in conjunction with ATA Data Setup, ATA Data Assertion,
ATA Data Recover, and PIO Mode Selection fields.
0
1
Bit (2)
Enable for the DRV_PWR_VALID pin. Drive Power Valid should only be
enabled in cable applications where the ISD-300A1 is VBUS powered.
0
1
Bit(1)
PIO data read 3-state control. Enabling this will 3-state (hi-Z) the ATA data
bus during PIO read operations while addressing the data register. In most
applications this bit is set to ‘0’. This functionality is provided as a solution
for devices that erroneously drive the ATA data bus continuously during PIO
data register reads.
0
1
Bit (0) – read only
This bit reflects the current state of the I_MODE input pin.
Active low (“connector ground” indication)
Active high (power indication from device)
Use timing information acquired from the Drive
Override device timing information with configuration values
pin disabled (most systems)
pin enabled
Normal operation as per ATA/ATAPI interface specification.
3-state (hi-Z) DD[15:0] during PIO data register reads.
010
001
001
001
000
(2+1)*33.33 = 133 ns
(1+1)*33.33 = 66 ns
(1+1)*33.33 = 66 ns
(1+1)*33.33 = 66 ns
(0+1)*33.33 = 33 ns
12
Description
ISD-300A1
ROM Defaults
On-board
0x40

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