SI2438FT18-EVB Silicon Laboratories Inc, SI2438FT18-EVB Datasheet - Page 80
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SI2438FT18-EVB
Manufacturer Part Number
SI2438FT18-EVB
Description
BOARD EVAL SI2438+SI3018 24PIN
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3050-E-FM.pdf
(128 pages)
Specifications of SI2438FT18-EVB
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 80 of 128
- Download datasheet (888Kb)
Si3050 + Si3011/18/19
Register 23. Ring Validation Control 2
Reset settings = 0010_1101
80
Bit
6:3
2:0
7
Name
Type
Bit
RCC[2:0]
RTO[3:0]
RDLY[2]
Name
RDLY[2]
R/W
D7
Ring Delay Bit 2.
This bit, in combination with the RDLY[1:0] bits (Register 22), sets the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring
threshold crossing.
RTO[3:0]
0000
0001
0010
1111
Ring Confirmation Count.
These bits set the amount of time that the ring frequency must be within the tolerances set
by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal.
RCC[2:0]
000
001
010
011
100
101
110
111
...
...
0
0
0
1
D6
RDLY[1:0]
Ring Timeout
1920
Ring Confirmation Count Time
DO NOT USE THIS SETTING
00
128
256
10
11
01
D5
m
m
100
150
200
256
384
512
640
1024
m
s
s
s
RTO[3:0]
m
m
m
m
m
m
m
R/W
m
s
s
s
s
s
s
s
s
Rev. 1.4
Delay
256
1792
512
0
m
D4
s
m
m
m
s
s
s
Function
D3
D2
RCC[2:0]
R/W
D1
D0
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