USBN9602-28M National Semiconductor, USBN9602-28M Datasheet - Page 25

• Manufacturer Part Number: USBN9602-28M
• Manufacturer: National Semiconductor

Specifications of USBN9602-28M

• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC W
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

11.0 Register Set
“NodeReset” is the USB Reset state. This is entered upon
a module reset or by software upon detection of a USB
Reset. Upon entry, all Endpoint Pipes are disabled.
EPC0.DEF and FAR.AD_EN should be cleared by the
software upon entry into this state. Upon exit from this
state, EPC0.DEF should be set so that the device re-
sponds to the default address.
“NodeResume” is the state in which Resume “K” signal-
ling is generated. The firmware should cause a transition
to this state to initiate a remote wake-up sequence by the
device. The node must remain in this state for at least 1
ms and no more than 15 ms.
“NodeOperational” is the normal operational state. In this
state the node is configured for operation on the USB.
“NodeSuspend” is the device inactive state. The firmware
should cause a transition to this state upon detection of a
Suspend event while in the NodeOperational state. While
in the NodeSuspend state, the transceivers operate in
their low-power suspend mode. All Endpoint Controllers
and internal states remain frozen. Upon detection of bus
activity, the ALTEV.RESUME bit is set. In response, soft-
ware can cause an entry to the NodeOperational state.
11.6 Main Event Register (MAEV)
11.6.1 WARN
FIFO Warning. One of the unmasked bits in the FIFO
Warning Event register has been set. The WARN bit is
cleared by reading the FIFO Warning Event Register.
11.6.2 ALT
Alternate Event. One of the unmasked bits in the Alter-
nate Event register has been set. The ALT bit is cleared
when the Alternate Event register is read.
11.6.3 TX_EV
Transmit Event. This bit is set if any of the unmasked bits
in the Transmit Event register (TXFIFOx or TXUNDRNx)
are set. Therefore, it indicates that an IN transaction has
been completed. This bit is cleared when all the
TX_DONE bits and the TXUNDRN bits in each Transmit
Status register are cleared.
11.6.4 FRAME
Frame event. This bit is set if the frame counter is updated
with a new value. This can be due to a valid SOF packet
being received on the USB or due to an artificial update if
the frame counter was unlocked or a frame was missed.
This bit is cleared when the register is read.
INTR RX_EV ULD NAK FRAME TX_EV ALT WARN
bit 7
see
text
0
bit 6
0
r
CoR
bit 5 bit 4
0
0
r
(Continued)
CoR
bit 3
0
bit 2
0
r
bit 1
0
r
bit 0
0
r
25
11.6.5 NAK
NAK Handshake. This bit is set if one of the unmasked
NAK Event register bits has been set. This bit is cleared
when the NAK Event register is read.
11.6.6 ULD
Unlock Locked Detected. If set, this bit indicates that the
Frame Timer has entered the unlocked state from a
locked condition, or has re-entered the locked condition
from an unlocked condition, as determined by the Un-
locked Status bit (FN.UL) being currently set. This bit is
cleared when the register is read.
11.6.7 RX_EV
Receive Event. This bit is set if any of the unmasked bits
in the Receive Event register are set. It indicates that a
SETUP or OUT transaction has been completed. This bit
is cleared when all of the RX_LAST bits in each of the re-
ceive status registers and all of the RXOVRRN bits in the
receive event register are cleared.
11.6.8 INTR
Master Interrupt Enable. This bit is hard-wired to zero in
the Main Event register. However, the corresponding bit in
the Main Mask register is the master interrupt enable.
11.7 Main Mask Register (MAMSK)
A bit is set to 1 in the Main Mask register enables gener-
ation of an interrupt on the occurrence of the respective
event in the Main Event register. Interrupt generation is
disabled otherwise. For information on the individual inter-
rupt events, see the description of the Main Event register.
11.8 Alternate Event Register (ALTEV)
11.8.1 SD3
Suspend Detect 3 ms. This bit is set after 3 milliseconds
of idle time is detected on the upstream port, indicating
that the device should be suspended. The suspend oc-
curs under firmware control by writing the SUSPEND val-
ue to the NFS register. The SD3 bit is cleared when the
register is read.
INTR RX_EV ULD NAK FRAME TX_EV ALT WARN
bit 7
RESUME RESET SD5 SD3 EOP
0
CoR
bit 7
0
bit 6
0
CoR
bit 6
bit 5 bit 4
0
0
CoR CoR CoR
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0
0
r/w
bit 3
0
0
0
bit 2
0
www.national.com
bit 1
0
res
–
–
bit 0
0