SI4707-B20-GM Silicon Laboratories Inc, SI4707-B20-GM Datasheet
SI4707-B20-GM
Specifications of SI4707-B20-GM
SI4707-B20-GM
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SI4707-B20-GM Summary of contents
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... ADC DAC LOUT PGA DSP ADC DAC ROUT RSSI / GPO GPO SAME SNR CONTROL INTERFACE Copyright © 2008 by Silicon Laboratories Si4707-B20 R ECEIVER Ordering Information: See page 22. Pin Assignments Si4707-B20-GM (Top View FMI 2 15 NP2 RFGND 3 GND 14 PAD NP1 4 13 RST 5 12 ...
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... Si4707-B20 2 Rev. 0.8 ...
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... GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.11. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.12. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. Pin Descriptions: Si4707-B20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8. Package Markings (Top Marks 8.1. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9. Package Outline: Si4707 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 ...
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... Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4707 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. ...
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... SCLK, RCLK inactive IOPD V 0.7 x VIO VIO = 3 3 500 µA 0.8 x VIO OH OUT –500 µA OL OUT Rev. 0.8 Si4707-B20 Min Typ Max Unit — 19 — 320 600 µA — µA — µA — — — — 0.3 x VIO –10 — 10 µA –10 — ...
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... Si4707-B20 Table 4. Reset Timing Characteristics (V = 2 1 Parameter RST Pulse Width and GPO1, GPO2/INT Setup to RST↑ GPO1, GPO2/INT Hold from RST↑ Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST ...
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... RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4707 delays SDIO by a minimum of 300 ns from the V specification. 5. The maximum t ...
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... Si4707-B20 SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read and Write Timing Diagram HIGH t r:IN f: HD:DAT SU:DAT D7-D0 ACK DATA ACK Rev ...
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... HSDIO HIGH LOW t S A6-A5, R/W, A0 D15 A4-A1 Address HSDIO CDV t S A6-A5, R/W, A0 D15 A4-A1 Address In ½ Cycle Bus Turnaround Rev. 0.8 Si4707-B20 Min Typ Max Unit 0 — 2.5 MHz 25 — — — — — — — — — — ...
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... Si4707-B20 Table 7. SPI Control Interface Characteristics (V = 2 1 Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLK↑ Setup SDIO Input to SCLK↑ Hold ↓ SEN Input to SCLK Hold ↓ SCLK to SDIO Output Valid ↓ ...
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... REFCLK Crystal Oscillator Frequency Crystal Frequency Tolerance Board Capacitance *Note: The Si4707 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. See AN332, Table 6 for more details °C) Symbol ...
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... To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 6. Pin 2 connects to the WB antenna interface. 7. Place Si4707 as close as possible to antenna jack and keep the FMI trace as short as possible ...
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... Bill of Materials Component(s) C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R U1 Si4707 WB + SAME Receiver C2, C3 Crystal load capacitors, 22 pF, ±5%, COG (Optional: for crystal oscillator option) X1 32.768 kHz crystal (Optional: for crystal oscillator option) Value/Description Optional Components Rev. 0.8 Si4707-B20 Supplier Murata Silicon Laboratories ...
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... OSC Figure 8. Functional Block Diagram The high integration and complete system production test simplifies design in, increases system quality, and improves manufacturability. The Si4707 is a feature-rich solution including 1050 tone detection, automatic frequency control, dynamic channel bandwidth filters, and digital tuning. In addition, ...
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... The Si4707 device stores the entire SAME message and provides a user programmable interrupt at the end of message detected, start of message detected, preamble detected, and/or header buffer ready. It also reports on the confidence level of each byte of data with a value of 0– ...
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... The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4707 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal ...
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... SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4707 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time ...
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... Summary,” on page 19. Properties are a special command argument used to modify the default chip operation and are generally configured immediately after powerup. A complete list of properties is available in Table 12, “Si4707 Property functions. Summary,” on page 20. Responses provide the user information and are echoed after a command and associated arguments are issued ...
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... Commands and Properties Table 11. Si4707 Command Summary Cmd Name 0x01 POWER_UP 0x10 GET_REV 0x11 POWER_DOWN 0x12 SET_PROPERTY 0x13 GET_PROPERTY 0x14 GET_INT_STATUS 0x15 PATCH_ARGS 0x16 PATCH_DATA 0x50 WB_TUNE_FREQ 0x52 WB_TUNE_STATUS 0x53 WB_RSQ_STATUS 0x54 WB_SAME_STATUS 0x55 WB_ASQ_STATUS 0x57 WB_AGC_STATUS 0x58 WB_AGC_OVERRIDE 0x80 GPO_CTL ...
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... WB_ASQ_INTERRUPT_ 0x5600 SOURCE WB_SAME_INTERRUPT_ 0x5500 SOURCE 20 Table 12. Si4707 Property Summary Description Enables interrupt sources. Sets frequency of reference clock in Hz. The range is 31130 to 34406 disable the AFC. Default is 32768 Hz. Sets the prescaler value for RCLK input. Sets the output volume. Mutes the audio output. L and R audio outputs may be muted independently in FM mode ...
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... Pin Descriptions: Si4707-B20 FMI RFGND NP1 RST Pin Number(s) Name connect. Leave floating. 2 FMI WB RF input. FMI should be connected to the antenna trace. 3 RFGND RF ground. Connect to ground plane on PCB. 4 NP1 Unused. Recommend connect to ground. 5 RST Device reset (active low) input. 6 SEN Serial enable input (active low). ...
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... Si4707-B20 7. Ordering Guide Part Number* Si4707-B20-GM WB Radio and SAME Receiver *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 22 Description Rev. 0.8 Package Operating Type Temperature QFN – °C Pb-free ...
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... Line 3 Marking: Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Workweek 0720 BTTT YWW 07= Si4707 20 = Firmware Revision 2 Revision B Die Internal tracking code Pin 1 Identifier Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. Rev. 0.8 Si4707-B20 ...
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... Si4707-B20 9. Package Outline: Si4707 QFN Figure 9 illustrates the package details for the Si4707. Table 13 lists the values for the dimensions shown in the illustration. Figure 9. 20-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.50 0.55 A1 0.00 0.02 b 0.20 0.25 c 0.27 0. ...
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... PCB Land Pattern: Si4707 QFN Figure 10 illustrates the PCB land pattern details for the Si4707-GM. Table 14 lists the values for the dimensions shown in the illustration. Figure 10. PCB Land Pattern Rev. 0.8 Si4707-B20 25 ...
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... Si4707-B20 Table 14. PCB Land Pattern Dimensions Symbol Millimeters Min 2.10 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last name, company, NDA reference number, and mysilabs user name to fminfo@silabs.com. Silicon Labs recommends an all lower case user name. Si4707-B20 Rev. 0.8 27 ...
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... Revision 0.1 to Revision 0.8 Updated Table 5, “2-Wire Control Interface 1,2,3 Characteristics ,” on page 7. Updated Table 8, “WB Receiver Characteristics page 11. Updated Table 11, “Si4707 Command Summary,” on page 19. Updated the title of AN383 to ”Si47xx Antenna, Schematic, Layout, and Design Guidelines.” ,” on Rev. 0.8 ...
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... N : OTES Si4707-B20 Rev. 0.8 29 ...
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... Si4707-B20 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...