AD8196-EVAL Analog Devices Inc, AD8196-EVAL Datasheet

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... Outputs can be set to a high impedance state to reduce the power dissipation and/or allow the construction of larger arrays using the wire-OR technique. The AD8196 is provided in a space-saving, 56-lead, LFCSP, surface-mount, Pb-free, plastic package and is specified to operate over the −40°C to +85°C temperature range. ...

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... High Speed Device Modes Register......................................... 16 Auxiliary Device Modes Register............................................. 16 Receiver Settings Register ......................................................... 17 Input Termination Pulse Register ............................................ 17 Receive Equalizer Register ........................................................ 17 Transmitter Settings Register.................................................... 17 Application Notes ........................................................................... 18 Pinout........................................................................................... 18 Cable Lengths and Equalization............................................... 19 The AD8196 as a Single-Channel Buffer ................................ 19 PCB Layout Guidelines.............................................................. 19 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 Rev Page ...

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... Outputs enabled, maximum pre-emphasis 4 Input termination on Output termination on, no pre-emphasis Output termination on, maximum pre-emphasis Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis High speed switching register: HS_CH All other configuration registers Rev Page AD8196 Min Typ Max Unit 2.25 Gbps − (p-p) 1 ...

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... Differential interpair skew is measured between the TMDS pairs of a single link. 2 AD8196 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. ...

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... IN MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the < AMUXVCC + 0 AD8196 is limited by the associated rise in junction tempera- < DVCC + 0 ture. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package ...

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... AD8196 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE AD8196 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO MEET THERMAL SPECIFICATIONS. Table 4. Pin Function Descriptions Pin No. ...

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... Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. Power Negative Digital and Auxiliary Switch Power Supply nominal. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. Rev Page AD8196 ...

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... Figure 4. Test Circuit Diagram for RX Eye Diagrams Figure 7. RX Eye Diagram at TP3 (Cable = AWG) Figure 8. RX Eye Diagram at TP3 (Cable = AWG) Rev Page − 1, data rate = 2.25 Gbps, unless otherwise noted. AD8196 SERIAL DATA EVALUATION ANALYZER BOARD SMA COAX CABLE TP3 ...

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... Figure 9. Test Circuit Diagram for TX Eye Diagram Figure 12. TX Eye Diagram at TP3 (Cable = AWG) Figure 13. TX Eye Diagram at TP3 (Cable = AWG) Rev Page − 1, data rate = 2.25 Gbps, unless otherwise noted. HDMI CABLE SERIAL DATA ANALYZER TP3 0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps AD8196 ...

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... AD8196 T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing = A 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 0.6 2m CABLE = 30AWG 5m TO 20m CABLES = 24AWG 0.5 0.4 0.3 1 ...

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... Figure 24. Differential Input Termination Resistance vs. Temperature 60 80 100 Rev Page − 1, data rate = 2.25 Gbps, unless otherwise noted. DJ (p-p) RJ (rms) 0 2.5 2.7 2.9 3.1 3.3 INPUT COMMON-MODE VOLTAGE (V) Figure 23. Jitter vs. Input Common-Mode Voltage –40 – TEMPERATURE (°C) AD8196 3.5 3.7 80 100 ...

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... This mode is enabled by programming the HS_EN bit of the high speed device modes register. Larger wire- OR’ arrays can be constructed using the AD8196 in this mode. The AD8196 requires output termination resistors when the high speed outputs are enabled. Termination can be internal and/or external ...

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... AUX Figure 27. Auxiliary Channel Simplified Schematic Showing AUX_A0 to AUX_COM0 Routing When turning off the AD8196, care needs to be taken with the AMUXVCC supply to ensure that the auxiliary multiplexer pins are in a high impedance state. A scenario that illustrates this requirement is one where the auxiliary multiplexer is used to switch the display data channel (DDC) bus ...

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... Send a start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low). 2. Send the AD8196 part address (seven bits). The upper six bits of the AD8196 part address are the static value [100100] and the LSB is set by Input Pin I2C_ADDR. This transfer should be MSB first. 3. ...

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... This transfer should be MSB first. 9. Send the read indicator bit (1). 10. Wait for the AD8196 to acknowledge the request. 11. The AD8196 serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. This data is sent MSB first. 12. Acknowledge the data from the AD8196. ...

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... AD8196 CONFIGURATION REGISTERS The serial interface configuration registers can be read and written using the I 2 The LSB of the AD8196 I C part address is set by tying Pin I2C_ADDR to 3.3 V (I2C_ADDR = (I2C_ADDR = 0). Table 5. Register Map Name Bit 7 Bit 6 High Speed High speed Device switch enable ...

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... TX_PTO: High Speed (TMDS) Output Termination On/Off Select Bit (All Channels) Table 16. TX_PTO Description TX_PTO Description 0 Output termination off 1 Output termination on TX_OCL: High Speed (TMDS) Output Current Level Select Bit (All Channels) Table 17. TX_OCL Description TX_OCL Description 0 Output current set Output current set Rev Page AD8196 ...

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... AD8196 fully buffers and electrically decouples the outputs from the inputs. Therefore, the effects of the vias placed on the output signal lines are not seen at the input of the AD8196. The programmable output terminations also improve signal quality at the output of the AD8196. The PCB designer, there- ...

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... PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8196, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. ...

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... Ground Current Return In some applications, it can be necessary to invert the output pin order of the AD8196. This requires a designer to route the TMDS traces on multiple layers of the PCB. When routing dif- ferential pairs on multiple layers necessary to also reroute the corresponding reference plane to provide one continuous ground current return path for the differential signals ...

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... The unselected auxiliary inputs of the AD8196 are placed into a high impedance mode when the device is powered up. To ensure that all of the auxiliary inputs of the AD8196 are in a high impedance mode when the device is powered off necessary to power the AMUXVCC supply as illustrated in Figure 28. ...

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... RECOMMENDED NOT RECOMMENDED Figure 34. Recommended Pad Outline for Bypass Capacitors In applications where the AD8196 is powered by a single 3.3 V supply recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF capacitors ...

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... DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. ORDERING GUIDE Temperature Model Range 1 AD8196ACPZ −40°C to +85°C 1 AD8196ACPZ-R7 −40°C to +85°C 1 AD8196ACPZ-RL −40°C to +85°C AD8196-EVAL Pb-free part. 8.00 BSC SQ 0.60 MAX 43 42 TOP 7.75 VIEW BSC SQ 0.50 0.40 ...

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... AD8196 NOTES Purchase of licensed 2 components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components in an ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...