SI5374B-A-GL Silicon Laboratories Inc, SI5374B-A-GL Datasheet - Page 26

Clock Synthesizer / Jitter Cleaner QUAD DSPLL JITT ATT CLK LO LP BW 8IN/OUT

SI5374B-A-GL

Manufacturer Part Number
SI5374B-A-GL
Description
Clock Synthesizer / Jitter Cleaner QUAD DSPLL JITT ATT CLK LO LP BW 8IN/OUT
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5374B-A-GL

Package / Case
PBGA-80
Input Level
LVCMOS
Max Input Freq
525 Hz
Max Output Freq
808 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Outputs
8
Output Level
LVCMOS
Supply Current
1100 mA
Supply Voltage (max)
2.8 V
Supply Voltage (min)
- 0.5 V
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5374B-A-GL
Manufacturer:
SILICON
Quantity:
1 001
Part Number:
SI5374B-A-GL
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Si5374
Reset value = 0000 0000
Reset value = 0100 0000
26
Register 10.
Register 11.
Name
Name
Type
Type
7:4
1:0
7:2
Bit
Bit
Bit
Bit
3
2
1
0
DSBL2_REG DSBL2_REG.
DSBL1_REG DSBL1_REG.
Reserved
Reserved
Reserved
PD_CK2
PD_CK1
D7
Name
Name
R
D7
R
D6
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the NC2 output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the NC1 output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
R
D6
R
D5
R
D5
R
Preliminary Rev. 0.4
D4
R
D4
R
DSBL2_REG
R/W
D3
Function
Function
D3
R
DSBL1_REG
R/W
D2
D2
R
PD_CK2
R/W
D1
D1
R
PD_CK1
R/W
D0
D0
R

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