NOIL2SC1300A-GDC ON Semiconductor, NOIL2SC1300A-GDC Datasheet
NOIL2SC1300A-GDC
Specifications of NOIL2SC1300A-GDC
Related parts for NOIL2SC1300A-GDC
NOIL2SC1300A-GDC Summary of contents
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... The LUPA1300-2 is housed in a 168 pin mPGA package and is available in a monochrome version and Bayer (RGB) patterned color filter array. The monochrome version is also available without glass. Contact your local ON Semiconductor office. ORDERING INFORMATION Marketing Part Number NOIL2SM1300A-GDC NOIL2SM1300A-GWC NOIL2SC1300A-GDC © Semiconductor Components Industries, LLC, 2011 July, 2011 − Rev. 8 • Medical Imaging • Industrial Imaging 2 ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . ...
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... Operating ratings are conditions at which operation of the device is intended to be functional Semiconductor recommends that our customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation. ...
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Electrical Specifications Table 4. POWER SUPPLY RATINGS Boldface limits apply for MIN Symbol Power Supply V , GND Analog Supply Operating Voltage ANA ANA Dynamic Current Peak Current Standby Current V , GND Digital ...
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Table 4. POWER SUPPLY RATINGS Boldface limits apply for MIN Symbol Power Supply V Antiblooming Operating Voltage RES_AB (Note 4) Supply Dynamic Current Peak Current following edge reset Standby Current V Reset Dual Operating ...
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Table 6. AC ELECTRICAL CHARACTERISTICS The following specifications apply for VDD = 2.5 V, Clock = 315 MHz, 500 fps. Symbol Parameter F Input Clock Frequency CLK DC Clock Duty Cycle CLK DCD Duty Cycle Distortion Jitter fps Frame Rate ...
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Spectral Response Curve 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 400 500 Figure 3. Spectral Response of LUPA1300−2 Mono and Color 600 700 800 Wavel ength (nm ) http://onsemi.com 900 1000 ...
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Color Filter Array The color version of LUPA1300-2 is available in Bayer (RGB) patterned color filter array. The orientation of RGB is shown in Figure 4. Figure 4. RGB Bayer http://onsemi.com 8 ...
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Image Sensor Core The floor plan of the architecture is shown in Figure 5. The sensor consists of a pixel array, analog front end, data block, and LVDS transmitters and receivers. Separate modules for the SPI, clock division, and sequencer ...
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Analog Front End Programmable Gain Amplifiers The PGAs amplify the signal before sending it to the ADCs. The amplification inside the PGA is controlled by one SPI setting: afemode [5:3]. Six gain steps can be selected by the afemode<5:3> register. ...
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LVDS Block The LVDS block is positioned below the data block. It receives a differential clock signal, transmits differential data over the 12 data channels, and transmits a LVDS clock signal and a synchronization signal over the clock and synchronization ...
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Table 9. INTERNAL REGISTERS Block Register Name Address [6..0] AFE afepwd2 12 Bias block bandgap 13 Image imcmodes 14 Core Fix7 15 Fix8 16 imcbias1 17 imcbias2 18 imcbias3 19 Imcbias4 20 Data Block Fix9 21 Fix10 22 dataconfig1 23 ...
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Table 9. INTERNAL REGISTERS Block Register Name Address [6..0] Data Block datachannel0_2 31 datachannel1_1 32 datachannel1_2 33 datachan- 54 nel12_1 datachan- 55 nel12_2 Sequencer seqmode1 56 seqmode2 57 seqmode3 58 Field Reset Value [7:0] 0x00 Pattern inserted to generate a ...
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Table 9. INTERNAL REGISTERS Block Register Name Address [6..0] Sequencer seqmode4 59 window1_1 60 window1_2 61 window1_3 62 window1_4 63 window2_1 64 window2_2 65 window2_3 66 window2_4 67 window3_1 68 window3_2 69 window3_3 70 window3_4 71 window4_1 72 window4_2 73 ...
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Table 9. INTERNAL REGISTERS Block Register Name Address [6..0] tint_ds_timer1 81 tint_ds_timer2 82 tint_ts_timer1 83 tint_ts_timer2 84 tint_black_timer 85 rot_timer 86 fot_timer 87 fot_timer 88 prechpix_timer 89 prechpix_timer 90 prechcol_timer 91 rowselect_timer 92 sample_timer 93 sample_timer 94 vmem_timer 95 vmem_timer ...
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Data Block The data block is positioned in between the analog front end (output stage + ADCs) and the LVDS interface. It muxes the outputs of 2 ADCs to one LVDS block and performs some minor data handling: • CRC ...
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Y2_start (64 and 65, 10 bit). These registers set the Y start address for window 2 (if enabled). X2_start (65, 6bit). This register sets the X start address for window 2 (if enabled). Y2_end (66 and 67, 10 bit). These ...
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... Number of pixels read out each line Clock Period 1/63 MHz = 15.9 ns NOTE: For more information on FPS calculation, refer the ON Semiconductor application note AN57864. In global shutter mode, the whole pixel array is integrated simultaneously including the dummy line for FPN correction. Windowing Windowing is easily achieved by SPI. The starting point of the x and y address and the window size can be uploaded ...
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Operation and Signaling Digital Signals Depending on the operation mode (Master or Slave), the pixel array of the image sensor requires different digital control signals. The function of each signal is listed in this table. Table 12. OVERVIEW OF DIGITAL ...
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The timing of the sensor consists of two parts. The first part is related to the exposure time and the control of the pixel. The second part is related to the read out of the image sensor. Integration and readout ...
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Programming the Exposure Time In master mode, the exposure time is configured in two distinct methods (controlled by register seqmode3[6]): • # lines: Obvious, changing signals that control integration time. They are always changed during ROT to avoid any image ...
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Slave Mode In slave mode, the register values of res_length and tint_timer are ignored. The integration time is controlled by the int_time pin. The relationship between the input pin and the integration time is shown in Figure 15. When the ...
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Master Mode In this mode, a rising edge on int_time1 pin is used to trigger the start of integration and read out. The tint_timer defines the integration time independent of the assertion of the input pin int_time1. After the integration ...
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Image Format and Read Out Protocol The active area read out by the sequencer in full frame mode is shown in Figure 18. Before the actual pixels are read out, one dummy line is read to enable column FPN correction. ...
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The following sections discuss the appearance of the output (data and synchronization codes) in several relevant configurations. Twelve output channels are connected to the 24 ADCs and handle the data. One additional channel contains all the synchronization codes for the ...
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Table 16. REMAPPING SCHEME FOR ONE ROW timeslot ch0 ch1 ch2 54b 1294 1292 1290 CRC Table 17. REMAPPING SCHEME FOR ONE ROW IN REVERSE X/Y READOUT MODE Timeslot ch0 ch1 ch2 54a 1295 1293 1291 54b 1294 1292 1290 ...
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Single Window Mode Containing Timeslot 54 In this operation mode, only part of the sensor is read out, as shown by the shaded area in Figure 19. A clear distinction is made with the single window mode that does not ...
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Single Window Mode Not Containing Timeslot 54 In this operation mode, only part of the sensor is read out, as shown in Figure 21. Although the window is defined as Figure 21. Single Window Not Containing Timeslot 54 Figure 22 ...
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Windowing A fully configurable window can be selected for readout. y star start The parameters to configure this window are: x_start. The sensor reads out 24 pixels in one single clock cycle. The granularity of ...
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Reverse Scan Reverse scanning is supported in the X and Y direction. Line 0 (first line on the output) is the top line in normal mode and the bottom line in reverse scanning, as shown in Figure 24 ...
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Figure 27 shows the sequence of integration and read out for multiple windows. The handling of integration time is identical to the single window mode (except that in this case, the maximum integration time is equal to the sum of ...
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The reset levels are configured through external (power) pins. In master mode, the time stamps of the double and triple slope resets are configured in a method similar to configuring the exposure time. The time stamps are enabled Figure 29. ...
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Column FPN Correction The column FPN of the sensor is improved by the offset correction of the columns. At the start of every frame, before read out of the actual lines is done, a fixed voltage is applied at the ...
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Full Frame Mode In this operation mode, the entire sensor shown in Figure 18 on page 24 is read out. Figure 33 shows the Sequencer FOT ROT internal state Data channel Sync Channel Data Channel T Sync Channel T Sequencer FOT ROT ...
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Pin List Table 20. PIN PLACEMENT LAYOUT (Top View 134 130 127 124 121 118 115 B * 131 128 125 122 119 116 C 133 132 129 126 123 120 117 D ...
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Table 21. PIN LIST Pin No. Pin Name Type 1 clkoutp LVDS 2 clkoutn LVDS 3 chp[0] LVDS 4 chn[0] LVDS 5 gndlvds Supply 6 gndadc Supply 7 vddadc Supply 8 vddlvds Supply 9 chp[1] LVDS 10 chn[1] LVDS 11 ...
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Table 21. PIN LIST Pin No. Pin Name Type 43 vddadc Supply 44 vddlvds Supply 45 clkinp LVDS 46 clkinn LVDS 47 syncp LVDS 48 syncn LVDS 49 gnddig Supply 50 vdddig Supply 51 cap_vrefm Analog 52 cap_vrefp Analog 53 ...
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Table 21. PIN LIST Pin No. Pin Name Type 83 vpix Supply 84 pixdiode Analog 85 gndpix Supply 86 vsamp Supply 87 vresetab Supply 88 vprech Supply 89 vmemh Supply 90 vmeml Supply 91 vreset Supply 92 vresetds Supply 93 ...
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Table 21. PIN LIST Pin No. Pin Name Type 124 cap_vrefcm Analog 125 vpix Supply 126 cap_vrefadc Analog 127 spics CMOS 128 spiclk CMOS 129 spiin CMOS 130 spiout CMOS 131 mbsbus[0] Analog 132 mbsbus[1] Analog 133 refbg Analog 134 ...
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Table 22. MECHANICAL SPECIFICATIONS Parameter Die Die thickness (Pin 1 is located Die position, X offset to the package center bottom left) Die position, Y offset to the package center Die position, X tilt Die position, Y tilt Die placement ...
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Package Drawing Figure 35. Package Outline Drawing for the LUPA1300−2 168−Pin mPGA http://onsemi.com 41 001−44705 *A ...
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... Figure 36 shows the transmission characteristics of the glass lid. Figure 36. Transmission Characteristics of the Glass Lid For proper handling and storage conditions, refer to the ON Semiconductor application note AN52561. ON Semiconductor’s Image Sensor Business Unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to Seller’ ...
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Acronym Description ADC Analog-to-Digital Converter AFE Analog Front End BL Black pixel data CDM Charged Device Model CDS Correlated Double Sampling CMOS Complementary Metal Oxide Semiconductor CRC Cyclic Redundancy Check DAC Digital-to-Analog Converter DDR Double Data Rate DNL Differential Non−Linearity ...
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A constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. Con- version gain = q/C where q is the charge of an electron (1.602E 19 Coulomb) and C is ...
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