NOII5SM1300A-QWC ON Semiconductor, NOII5SM1300A-QWC Datasheet
NOII5SM1300A-QWC
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NOII5SM1300A-QWC Summary of contents
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... Traffic monitoring ■ Ordering Information See Ordering Code Information on page 33 for more information. Marketing Part Number NOII5SM1300A-QDC NOII5SM1300A-QWC NOII5SC1300A-QDC NOII5FM1300A-QDC Semiconductor Components Industries, LLC, 2011 © June, 2011 - Rev. 9 IBIS5 1.3 Megapixel CMOS Image Sensor Description The IBIS5-1300 is a solid state CMOS image sensor that integrates the functionality of complete analog image acquisition, digitizer, and digital signal processing system on a single chip ...
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... Package Information ........................................................... 26 Pin List ............................................................................ 26 Pad Position and Packaging .......................................... 29 Package Drawing with Glass .......................................... 30 Glass Lid ........................................................................ 32 Handling Precautions .......................................................... 32 Limited Warranty ................................................................. 32 Return Material Authorization (RMA) ............................. 32 RoHS (Pb-free) Compliance ........................................... 32 Acceptance Criteria Specification ...................................... 32 Ordering Code Information ................................................. 33 Appendix A: IBIS5 Demo Kit ............................................... 33 Document History Page ...................................................... 34 Rev www.onsemi.com | Page NOII5SM1300A ...
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... Full Well Charge Temporal Noise Parasitic light sensitivity Dark noise Signal to Noise Ratio Fixed pattern noise (FPN) 4.5 LSB10 Dark signal [2] Description [1] Description Rev www.onsemi.com | Page NOII5SM1300A Parameter Specifications 8.4 V/lux.s at 650 nm - 62500 e 2.5 LSB10 3% - 21e 64 dB 5.5 LSB10/sec at 30 °C ...
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... N/A 34.5 mA N/A 10.5 mA N/A N/A N/A Condition V = VDD or GND IN VDD = min –100 µA OH VDD = min 100 µA OH System clock <= 40 MHz Rev www.onsemi.com | Page NOII5SM1300A Min Typ Max Unit +3.3 +4.5 +4.5 V +3.3 +4.5 +4.5 V +2.5 +3.0 +3.3 V +3.0 +3.3 +3 ...
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... Some basic signals (such as start/stop integration, line and frame sync signals) are generated externally. A 10-bit ADC is implemented on chip but electrically isolated from the image core. You must route the analog pixel output to the analog ADC input on the outside. Rev www.onsemi.com | Page NOII5SM1300A Sensor Reset C Select Sample ...
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... Note that this response curve includes the optical cross talk of the pixels. Figure 4. Color Filter Arrangement of Pixels R G1 (0,0) Figure 5. Spectral Response for IBIS5-1300 Color Rev www.onsemi.com | Page NOII5SM1300A Figure 5 shows the response of the color G2 B ...
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... Figure 6 shows the spectral response characteristic for the NOII5SM1300A and the NOII5FM1300A. The curve is measured directly on the pixels. It includes effects of non-sensitive areas in the pixel, for example, interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE × 30%, approximately around 650 nm. In view of a fill factor of 40%, the QE is thus close to 75% between 500 and 700 nm ...
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... Figure 7. Electro-Voltaic Response Curve 10000 20000 30000 40000 50000 # electrons on page 7. Various machine vision applications use light sources in the NIR, hence the NOII5FM1300A 0.37 0.18 0.16 0.07 0.26 0.16 0.13 0.11 Rev www.onsemi.com | Page NOII5SM1300A 60000 70000 80000 ...
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... The pixel array (VDDR_LEFT, VDDH and VDDC) analog supplies are especially vulnerable to this. Figure 8. Image Core SAMPLE RESET HOLD Pixel row Pixel Pixel A B Pixel column Column amplifiers Read-pointer BUS_A BUS_B X addressing Rev www.onsemi.com | Page NOII5SM1300A Vddreset VDDR_RIGHT Y-right addressing Y_START Y_CLOCK VDDC Output amplifier PXL_OUT ...
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... Each biasing signal determines the operation of a corresponding module in the sense that it controls the speed and power dissi- pation. The tolerance on the DC-level of the bias levels can vary ±150 mV due to process variations. Comment Rev www.onsemi.com | Page NOII5SM1300A Table 9 to achieve the best possible Description Typ Voltage on HOLD switches. ...
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... Activating Y_SWAP30 results in pattern ’OXOXOXOX’. Activating both Y_SWAP12 and Y_SWAP30 results in pattern ’OOXXOOXX’. The addressable pixel range when Y-sub sampling is enabled is: 0–1, 4–5, 8–9, 12–13, … 1020–1021 Rev www.onsemi.com | Page NOII5SM1300A Y_SWAP12 Y_SWAP30 Reg(n) Reg(n+1) SRH Reg(n+2) ...
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... DAC_VLOW. The range of the DAC is defined using a resistive division with R Figure 12. Internal and External ADC Connections 3. The internal resistor R The recommend resistor values for both DAC_VLOW and DAC_VHIGH are 0 . Rev www.onsemi.com | Page NOII5SM1300A Amplifier Register (6:0) Table DC Gain Bits DC Gain 1.37 1000 6.25 1 ...
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... ADC_VLOW). The values of the resistors depend on the value of R assure proper working of the ADC, make certain the voltage difference between ADC_VLOW and ADC_VHIGH is at least 1.0 V. Rev www.onsemi.com | Page NOII5SM1300A 13. Figure 13 shows this pipeline delay. has a value of approximately 585 . ADC ...
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... ADC output value. 3. Change DAC_FINE such that the average of the odd columns is almost same as the even columns. 4. Change DAC_RAW again such that all pixels have a non-zero output, but are as close to zero as possible. 5. Repeat for different gains. Rev www.onsemi.com | Page NOII5SM1300A ...
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... On power-on, all registers in the sensor are reset to zero. To start operating the sensor, first load all the registers using the parallel or serial-3-wire interface. The value to be loaded in each register on power-on is given in the table. Rev www.onsemi.com | Page NOII5SM1300A Common Sample & Hold Time Burst Readout ...
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... Swap columns 3-4, 7-8, … Enable sub-sampling in Y-direction Swap rows 1-2, 5-6, … Swap rows 3-4, 7-8, … Default value <6:0>: ’1010000’ Output amplifier gain setting 1 = Amplifier in unity gain mode 1 = Activates second output 0 = Amplifier in standby mode Rev www.onsemi.com | Page NOII5SM1300A Description ...
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... In normal (single slope) mode the pixel reset is controlled from the left side of the image core using the voltage applied on pin VDDR_LEFT as pixel reset voltage. In multiple slope opera- tion, apply one or more variable pixel reset voltages. Rev www.onsemi.com | Page NOII5SM1300A Description bits GRAN_SS_SEQ_MSB (bit ...
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... INT_TIME register (number of lines). The actual integration time is given by Tint Integration time [# lines] = NROF_LINES register – INT_TIME register. Tint Integration time [# lines] = NROF_LINES register – INT_TIME register ift Rev www.onsemi.com | Page NOII5SM1300A on page 17 lin llo ift Internal clock Figure 18). ...
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... The maximum tested frequency of S_DATA is 2.5 MHz.) The serial 2-wire interface is not operational in the IBIS5-1300 image sensor. Use the 3-wire SPI interface to load the sensor registers. Figure 19. Parallel Interface Timing Rev www.onsemi.com | Page NOII5SM1300A Output Amplifier SER_MODE Selected interface X Parallel ...
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... The external system generates these control signals with following time constraints to SYS_CLOCK (rising edge = active edge): T >7.5 ns SETUP T > 7.5 ns HOLD It is important that these signals are free of any glitches. Rev www.onsemi.com | Page NOII5SM1300A Table 20 Frame Frame Rate Readout Time Comment [frames/s] [ms Full resolution. ...
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... SS_START The SS-sequencer puts the image core in a readable state takes two granulated SS-sequencer clock periods The ’real’ integration or exposure time. int Figure 22. Global Shutter: Single Slope Integration Rev www.onsemi.com | Page NOII5SM1300A SS_START SS_STOP Y_CLOCK Y_START X_LOAD SYS_CLOCK ...
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... Figure 23. Global Shutter: Pixel Read Out Table 21. Row Blanking Time as Function of X-Sequencer Granularity Granularity N GRAN × 4 × 8 × 16 × 32 Figure 24. Pixel Output Rev www.onsemi.com | Page NOII5SM1300A T (µs) GRAN_X_SEQ × N × T MSB/LSB GRAN SYS_CLOCK 140 × 3.5 SYS_CLOCK 280 × ...
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... T upload registers. Kneepoint Table 24. T Enable Interface Mode 0 Parallel 1 Serial 3-wire Rev www.onsemi.com | Page NOII5SM1300A , otherwise, the change stable for Different Granularity Settings stable T (µs) stable = 5 × N × T GRAN SYS_CLOCK 160 × SYS_CLOCK 320 × SYS_CLOCK 640 × ...
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... Parallel interface Serial 3 Wire The actual time to load the register itself depends on the interface mode that is used. The parallel interface is the fastest. Figure 26. Rolling Shutter Operation Figure 27. Windowing in X-Direction Rev www.onsemi.com | Page NOII5SM1300A load for Different Interfaces load T (µs) load 1 (about 40 SYS_CLOCK cycles) 16 (at 2.5 MHz data rate) ...
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... All internal registers are set to ‘0’ after SYS_RESET is applied. Because all the IBIS5-1300 control signals are active high, apply a low level (before SYS_RESET occurs) to these pins at start up to avoid latch up. Figure 28. Windowing in Y-Direction Rev www.onsemi.com | Page NOII5SM1300A ...
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... Default: Connect to VDDA with R = 0. Analog reference input. Biasing of DAC for output dark level. Use this to set the output range of DAC. Default: Connect to GND A with R = 0. Analog output. Analog pixel output 1. Rev www.onsemi.com | Page NOII5SM1300A Table 26 Pin Description lists the pins and ...
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... Digital input. ADC clock (40 MHz). Digital output. ADC data output (MSB). Digital output. ADC data output. Digital output. ADC data output. Digital output. ADC data output. Digital output. ADC data output. Digital output. ADC data output. Rev www.onsemi.com | Page NOII5SM1300A Pin Description ...
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... Digital input. Data parallel interface (MSB). Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Rev www.onsemi.com | Page NOII5SM1300A Pin Description ...
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... Scribe lines take about 100 to 150 µm extra on each side. Pin 1 is located in the middle of the left side, indicated by a ‘1’ on the layout. A logo and some identification tags are on the top right of the die. Figure 29. IBIS5-1300 Bare Die Dimensions (All dimensions in µm) Test structure Rev www.onsemi.com | Page NOII5SM1300A Identification ...
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... Package Drawing with Glass Rev www.onsemi.com | Page NOII5SM1300A 001-07589 *A ...
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... Mechanical Specifications (see Min 0.500 1.520 – – 0.030 0.030 – – 1.270 Description Figure 31) Figure 30. Side View Dimensions Rev www.onsemi.com | Page NOII5SM1300A Package Drawing with Glass (mm) Typ Max 0.550 0.600 1.750 1.980 0.740 – 0.500 – 0.060 0.090 0.070 ...
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... Acceptance Criteria Specification in ESD-safe, clean The Product Acceptance Criteria is available on request. This document contains the criteria to which the IBIS5-1300 is tested before being shipped. Rev www.onsemi.com | Page NOII5SM1300A shows the transmission characteristics of the glass lid. ...
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... Figure 32. The IBIS5-1300 Demo Kit Rev www.onsemi.com | Page NOII5SM1300A D C Commercial Temperature Range D= 263 Glass, W=Windowless Q= LCC package Additional Functionality 1 ...
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... Document History Page Document Title: NOII5SM1300A IBIS5 1.3 Megapixel CMOS Image Sensor Orig. of Rev. ECN No. Change ** 310213 FVK *A 649064 FPW *B 1162847 FPW/ARI *C 1417584 FPW *D 2765859 NVEA *E 2786518 SHEA *F 2903130 NVEA *G 3056594 NVEA *H 3137684 NVEA 9 N/A SKW ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifi ...