A8296SESTR-T Allegro Microsystems Inc, A8296SESTR-T Datasheet - Page 13

• Manufacturer Part Number: A8296SESTR-T
• Description: IC REG LNB SGL SUPPLY 16-QFN
• Manufacturer: Allegro Microsystems Inc

Specifications of A8296SESTR-T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A8296
Interrupt Request (IRQ) pin
The A8296 provides an interrupt request pin (IRQ), which is an
open-drain, active low output. This output may be connected
to a common IRQ line with a suitable external pull-up resistor
and can be used with other I
attention from the master controller.
The IRQ output becomes active (logic low) when the A8296
recognizes a fault condition. The fault conditions that will force
IRQ active include undervoltage lockout (UVLO), overcurrent
protection (OCP), and thermal shutdown (TSD). The UVLO,
OCP, and TSD faults are latched in the Status register and will
not be unlatched until the A8296 Status register is successfully
transmitted to the master controller (an AK bit must be received
SDA
SCL
IRQ
Start
FAULT event, IRQ set low, Status register latched
A6
1
A5
2
A4
3
Chip Address
A3
4
Figure 7. Fault, IRQ, and Status Register Timing. When a FAULT occurs, the IRQ bit is set to low and the Status
register is latched. The IRQ bit is reset to high when the A8296 acknowledges it is being read. The Status register is
unlatched when the master acknowledges the status data from the A8296.
A2
5
A1
6
A0
7
2
C™ compatible devices to request
W
0
8
AK
Single LNB Supply and Control Voltage Regulator
9
acknowledge
from LNBR (slave)
RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
1
2
Status Register Address
3
4
5
6
7
8
AK
9
acknowledge
from LNBR (slave)
Stop
Start
from the master). See the description in the Status Register sec-
tion and figure 7 for further details.
When the master device receives an interrupt, it should address
all slaves connected to the interrupt line in sequence and read the
status register of each to determine which device is requesting
attention. As shown in figure 7, the A8296 latches all conditions
in the Status register and sets the IRQ to logic low when a fault
occurs. The IRQ bit is reset to logic high and the Status register is
unlatched when the master acknowledges the status data from the
A8296 (an AK bit must be received from the master).
The disable (DIS) and Power Not Good (PNG) conditions do not
cause an interrupt and are not latched in the Status register.
A6
1
A5
2
A4
3
Chip Address
A3
4
A2
5
A1
6
A0
7
R
1
8
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
AK
9
acknowledge
from LNBR (slave)
RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
1
2
3
Status Data
4
5
6
7
8
AK
9
acknowledge
from master
STATUS
register
unlatched
Stop
IRQ reset
13