ADG739BRU Analog Devices Inc, ADG739BRU Datasheet - Page 5

• Manufacturer Part Number: ADG739BRU
• Description: IC MUX/DEMUX DUAL 4X1 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Analog Multiplexerr

Specifications of ADG739BRU

• Rohs Status: RoHS non-compliant
• Function: Multiplexer/Demultiplexer
• Circuit: 2 x 4:1
• On-state Resistance: 4.5 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V
• Current - Supply: 10µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Package: 16TSSOP
• Maximum On Resistance: 11@3V Ohm
• Maximum High Level Output Current: 80 mA
• Multiplexer Architecture: 4:1
• Maximum Turn-off Time: 14(Typ)@3V ns
• Maximum Turn-on Time: 40(Typ)@3V ns
• Power Supply Type: Single

Model
ADG738BRU
ADG739BRU
ADG738
1
2
3
4, 5, 6, 7
8
9, 10, 11, 12
13
14
15
16
ADG739
1
3
4, 5, 6, 7
8, 9
10, 11, 12, 13 Sxx
14
15
16
2
Temperature Range
–40°C to +85°C
–40°C to +85°C
Mnemonic
SCLK
RESET
DIN
Sxx
Dx
V
GND
DOUT
SYNC
DD
RESET
SCLK
DIN
S1
S2
S3
S4
D
1
2
3
4
5
6
7
8
Function
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the
serial clock input. These devices can accommodate serial input rates of up to 30 MHz.
Active low control input that clears the input register and turns all switches to the OFF
condition.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the
serial clock input.
Drain. May be an input or output.
Source. May be an input or output.
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
Ground Reference.
Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of
the input shift register on the rising edge of SCLK. This is an open drain output which
should be pulled to the supply with an external resistor.
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift
register is enabled. Data is transferred on the falling edges of the following clocks.
Taking SYNC high updates the switch conditions.
Source. May be an input or output.
(Not to Scale)
TOP VIEW
ADG738
PIN FUNCTION DESCRIPTIONS
Package Description
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
PIN CONFIGURATIONS
ORDERING GUIDE
16
15
14
13
12
10
11
9
SYNC
DOUT
GND
V
S5
S6
S7
S8
DD
SCLK
SYNC
S1A
S2A
S3A
S4A
DIN
DA
1
2
3
4
5
6
7
8
(Not to Scale)
ADG739
TOP VIEW
16
15
14
13
12
10
11
9
DOUT
GND
V
S1B
S2B
S3B
S4B
DB
DD
ADG738/ADG739
Package Option
RU-16
RU-16