HV9982DB1 Supertex, HV9982DB1 Datasheet - Page 8

no-image

HV9982DB1

Manufacturer Part Number
HV9982DB1
Description
Manufacturer
Supertex
Datasheet

Specifications of HV9982DB1

Lead Free Status / Rohs Status
Supplier Unconfirmed
Fig. 13: Current Spike during PWM Dimming
Analog Control of PWM Dimming – The operation of the analog control of PWM dimming is shown in Figs. 14-16. Fig. 14
shows the waveforms for operation in one of the modes (S1=HI; S2=HI), with no external SYNC signal applied. The plots in
Figs. 15 and 16 show the operation with an external 350Hz synchronizing clock. Fig. 15 shows the waveforms with S1=HI
and S2=LO and Fig. 16 shows the waveforms with S1=HI and S2=HI. Fig. 17 shows the variation of the average LED cur-
rent with the voltage at the PWMD pin in these modes of operation.
Fig. 14: Analog Control of PWM Dimming w/o external clock (S1 = HI and S2 = HI)
Fig. 15: Analog Control of PWM Dimming synchronized to external clock (S1 = HI and S2 = LO)
Fig. 16: Analog Control of PWM Dimming synchronized to external clock (S1 = HI and S2 = HI)
C1 (Yellow): PWM Dimming Input for Channel 1(5V/div)
C4 (Green):
Time Scale: 500ns/div
C4 (Green):
C3 (Blue):
Time Scale:
C2 (Pink):
C3 (Blue):
C1 (Yellow): External SYNC signal (5V/div)
C4 (Green):
Time Scale:
C2 (Pink):
C3 (Blue):
C1 (Yellow): External SYNC signal (5V/div)
Time Scale:
C4 (Green):
Output Current for Channel 1 (50mA/div)
Output Current for Channel 1 (50mA/div)
RAMP voltage (2V/div)
1ms/div
Output Current for Channel 1 (50mA/div)
1ms/div
Signal at PWMD1 terminal (2V/div)
RAMP voltage (2V/div)
RAMP voltage (2V/div)
Output Current for Channel 1 (50mA/div)
1ms/div
Signal at PWMD1 terminal (2V/div)
8
HV9982DB1