DJLXT901ALC.A4 Cortina Systems Inc, DJLXT901ALC.A4 Datasheet - Page 9

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DJLXT901ALC.A4

Manufacturer Part Number
DJLXT901ALC.A4
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of DJLXT901ALC.A4

Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DJLXT901ALC.A4
Manufacturer:
Intel
Quantity:
10 000
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
PLCC
34
10
12
13
14
15
16
17
18
19
20
11
Table 1.
1
2
3
4
5
6
7
8
9
-
LQFP
10
56
12
13
14
15
18
19
21
22
23
24
25
26
27
28
29
34
35
36
11
9
LXT901/907 Signal Descriptions
AUTOSEL
Symbol
LEDT/
VCC1
VCC2
VCCA
CLKO
LEDR
TEST
TCLK
LEDL
CLKI
NTH
MD0
MD1
COL
PDN
RLD
TXD
TEN
CIN
JAB
CIP
LI
OD
OD
OD
I/O
O
O
O
O
O
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Power Inputs. Power supply inputs of +5 volts.
(LQFP Only)
AUI Collision Pair. Differential input to the AUI transceiver CI circuit. The input is
collision signaling or SQE.
Normal Threshold. Selects normal or reduced threshold.
When NTH is High, the normal twisted-pair squelch threshold is in effect.
When NTH is Low, the normal twisted-pair squelch threshold is reduced by 4.5 dB.
Mode Select 0 (MD0), Mode Select 1 (MD1). Mode select pins determine the
controller compatibility mode in accordance with
Remote Link Down. Output goes high to signal to the controller that the remote
port is in link down condition.
Link Test Enable. Controls Link Integrity Test; enabled when LI = High, disabled
when LI = Low
Jabber Indicator. Output goes High to indicate Jabber state.
Test. For Intel internal use only. It is recommended to tie this pin High externally.
Transmit Clock. A 10 MHz clock output. This clock signal should be directly
connected to the transmit clock input of the controller.
Transmit Data. Input signal containing NRZ data to be transmitted on the
network. Connect TXD directly to the transmit data output of the controller.
Transmit Enable. Enables data transmission and starts the watchdog timer.
Synchronous to TCLK (see Test Specifications for details).
Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a
20 MHz clock applied at CLKI with CLKO left open.
Collision Detect. Output which drives the collision detect input of the controller.
Automatic Port Select.
When High, automatic port selection is enabled (the 901/907 defaults to the AUI
port only if twisted-pair link integrity = Fail).
When Low, manual port selection is enabled (the PAUI pin determines the active
port).
Receive LED. Open drain driver for the receive indicator LED. Output is pulled
Low during receive.
Transmit LED (LEDT)/Power-Down (PDN). Open drain driver for the transmit
indicator. Output is pulled Low during transmit. Do not allow this pin to float. If
unused, tie High.
If externally pulled Low, the LXT901/907 goes to power-down state.
Link LED. Open drain driver for link integrity indicator. Output is pulled Low during
link test pass.
If externally tied Low, internal circuitry is forced to “Link Pass” state and the 901/
907 will transmit link test pulses continuously.
Universal 10BASE-T and AUI Transceivers — LXT901/907
Description
Table
2.
9

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