LFEC3E-3TN144I Lattice, LFEC3E-3TN144I Datasheet - Page 53

• Manufacturer Part Number: LFEC3E-3TN144I
• Description: IC FPGA 3.1KLUTS 97I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFEC3E-3TN144I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LatticeECP/EC Internal Switching Characteristics (Continued)
Lattice Semiconductor
t
t
t
PLL Parameters
t
t
DSP Block Timing
t
t
t
t
t
t
t
t
t
t
t
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
3. DSP Block is configured in Multiply Add/Sub 18 x 18 Mode.
4. These parameters include the Adder Subtractor block in the path.
Timing v.G 0.30
SUCE_EBR
HCE_EBR
RSTO_EBR
RSTREC
RSTSU
SUI_DSP
HI_DSP
SUP_DSP
HP_DSP
SUO_DSP
HO_DSP
COI_DSP
COP_DSP
COO_DSP
SUADSUB
HADSUB
Parameter
4
4
4
4
Clock Enable Setup Time to EBR Output
Register
Clock Enable Hold Time to EBR Output Register
Reset To Output Delay Time from EBR Output
Register
Reset Recovery to Rising Clock
Reset Signal Setup Time
Input Register Setup Time
Input Register Hold Time
Pipeline Register Setup Time
Pipeline Register Hold Time
Output Register Setup Time
Output Register Hold Time
Input Register Clock to Output Time
Pipeline Register Clock to Output Time
Output Register Clock to Output Time
AdSub Input Register Setup Time
AdSub Input Register Hold Time
2, 3
Description
Over Recommended Operating Conditions
3-17
-0.14
-0.38
-0.38
Min.
0.18
1.00
1.00
0.71
3.31
0.71
5.54
0.71
0.71
—
—
—
—
-5
Max.
DC and Switching Characteristics
1.47
7.50
4.66
1.47
LatticeECP/EC Family Data Sheet
—
—
—
—
—
—
—
—
—
—
—
—
-0.17
-0.30
-0.30
Min.
0.21
1.00
1.00
0.86
3.98
0.86
6.64
0.86
0.86
—
—
—
—
-4
Max.
1.76
9.00
5.60
1.77
—
—
—
—
—
—
—
—
—
—
—
—
-0.20
-0.23
-0.23
Min.
0.25
1.00
1.00
1.00
4.64
1.00
7.75
1.00
1.00
—
—
—
—
-3
10.50
Max.
2.05
6.53
2.06
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns