LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 5

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

QFNS
64-Pin QFNS
9 x 9 mm
0.90 mm height
0.50 mm pitch
48-Pin QFNS
7 x 7 mm
0.90 mm height
0.50 mm pitch
32-Pin QFNS
5 x 5 mm
0.85 mm height
0.50 mm pitch
24-Pin QFNS
4 x 4 mm
0.90 mm height
0.50 mm pitch
Chip Scale BGA
100-Ball csBGA
132-Ball csBGA
8 x 8 mm
1.23 mm height
0.50 mm pitch
144-Ball csBGA
7 x 7 mm
1.00 mm height
0.50 mm pitch
56-Ball csBGA
6 x 6 mm
1.23 mm height
0.50 mm pitch
64-Ball csBGA
5 x 5 mm
1.00 mm height
0.50 mm pitch
Ultra Chip Scale BGA
132-Ball ucBGA
6 x 6 mm
1.00 mm height
0.40 mm pitch
64-Ball ucBGA
4 x 4 mm
1.00 mm height
0.40 mm pitch
TQFP/PQFP
208-Pin PQFP
28 x 28 mm (body)
3.40 mm height
0.50 mm pitch
176-Pin TQFP
24 x 24 mm (body)
1.40 mm height
0.50 mm pitch
144-Pin TQFP
20 x 20 mm (body)
1.40 mm height
0.50 mm pitch
100-Pin TQFP
128-Pin TQFP
14 x 14 mm (body)
1.4 mm height
0.50 mm pitch (100 TQFP)
0.40 mm pitch (128 TQFP)
44-Pin TQFP
64-Pin TQFP
10 x 10 mm (body)
1.00 mm height (44 TQFP)
1.40 mm height (44 TQFP)
1.40 mm height (64 TQFP)
0.80 mm pitch (44 TQFP)
0.50 mm pitch (64 TQFP)
48-Pin TQFP
7 x 7 mm (body)
1.00 mm height
1.40 mm height
0.50 mm pitch
Wafer Level Chip Scale
49-Ball WLCSP
3.1 x 3.1 mm
0.59 mm height
0.40 mm pitch
25-Ball WLCSP
2.5 x 2.5 mm
0.59 mm height
0.40 mm pitch
Note: Packages shown actual size.
RoHS Compliant
and Halogen-Free
Packaging
Lattice Semiconductor is a leader in the
development of lead-free and halogen-
free packaging solutions. Both are RoHS
compliant.
For further information, see the RoHS
Compliant Packaging web page at:
www.latticesemi.com/rohs.
Users requiring leaded packaging are
requested to contact their local Lattice
sales office.
Package Diagrams
For detailed package schematics, down-
load the Package Diagrams document at
www.latticesemi.com/packaging.
Reflow Guidelines &
Moisture Sensitivity
For information on solder reflow and re-
work processes for Lattice surface mount
products, download TN1076, Solder
Reflow Guide for Surface Mount Devices
from the Lattice web site at
www.latticesemi.com/solderreflow.
Board Layout
Recommendations
TN1074, PCB Layout Recommendations
for BGA Packages, describes some of the
most common problems encountered
when working with BGA packages and
provides tips for avoiding them at the
design stage. Download TN1074 from the
Lattice web site at www.latticesemi.com/
boardlayout.
For more information and design examples
see the PCB Design Support web page at
www.latticesemi.com/pcbdesignsupport.
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