LFXP2-5E-5MN132C Lattice, LFXP2-5E-5MN132C Datasheet - Page 17

• Manufacturer Part Number: LFXP2-5E-5MN132C
• Description: IC FPGA 5KLUTS 86I/O 132-BGA
• Manufacturer: Lattice

Specifications of LFXP2-5E-5MN132C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1248

Lattice Semiconductor
Slice Clock Selection
Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing,
can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-13. Slice0 through Slice2 Clock Selection
Figure 2-14. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa-
tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
Secondary Clock
Secondary Clock
Primary Clock
Routing
Routing
Vcc
Vcc
12
12
8
4
1
3
1
2-14
25:1
16:1
Clock to Slice
Slice Control
LatticeXP2 Family Data Sheet
Architecture