LFXP2-8E-5MG132C Lattice, LFXP2-8E-5MG132C Datasheet - Page 18

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LFXP2-8E-5MG132C

Manufacturer Part Number
LFXP2-8E-5MG132C
Description
IC FPGA 8KLUTS 86I/O 132-BGA
Manufacturer
Lattice
Datasheet

Specifications of LFXP2-8E-5MG132C

Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Lattice Semiconductor
Figure 2-14. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa-
tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
Figure 2-15. Edge Clock Mux Connections
Secondary Clock
GPLL Output CLKOP
GPLL Output CLKOS
Clock Input Pad
GPLL Input Pad
GPLL Input Pad
Routing
Vcc
Input Pad
Input Pad
Routing
Routing
Routing
12
3
1
2-15
16:1
Top and Bottom
ECLK1/ ECLK2
Left and Right
Left and Right
(Both Muxes)
Edge Clocks
Edge Clocks
Edge Clocks
ECLK1
ECLK2
Slice Control
LatticeXP2 Family Data Sheet
Architecture

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