LFXP2-8E-5M132I Lattice, LFXP2-8E-5M132I Datasheet - Page 80
LFXP2-8E-5M132I
Manufacturer Part Number
LFXP2-8E-5M132I
Description
IC FPGA 8KLUTS 86I/O 132-BGA
Manufacturer
Lattice
Datasheet
1.LFXP2-40E-5FN484I.pdf
(92 pages)
Specifications of LFXP2-8E-5M132I
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number:
LFXP2-8E-5M132I
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SAMSUNG
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LFXP2-8E-5M132I
Manufacturer:
Lattice Semiconductor Corporation
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Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
For Left and Right Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
For Top and Bottom Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
P[Edge] [n+4]
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 16 bits
PICs Associated with
of data for the left and right edges and up to 18 bits of data for the top and bottom
edges. In some packages, all the potential DDR data (DQ) pins may not be available.
PIC numbering definitions are provided in the “Signal Names” column of the Signal
Descriptions table.
DQS Strobe
PIO Within PIC
4-3
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDR Strobe (DQS) and
Data (DQ) Pins
[Edge]DQSn
[Edge]DQSn
LatticeXP2 Family Data Sheet
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Pinout Information
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