LFEC15E-3FN484C Lattice, LFEC15E-3FN484C Datasheet - Page 36

• Manufacturer Part Number: LFEC15E-3FN484C
• Description: IC FPGA 10.2KLUTS 288I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFEC15E-3FN484C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1231

Lattice Semiconductor
Oscillator
Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master clock for configura-
tion. The oscillator and the master clock run continuously. The default value of the master clock is 2.5MHz. Table 2-
15 lists all the available Master Clock frequencies. When a different Master Clock is selected during the design pro-
cess, the following sequence takes place:
1. User selects a different Master Clock frequency.
2. During configuration the device starts with the default (2.5MHz) Master Clock frequency.
3. The clock configuration settings are contained in the early configuration bit stream.
4. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
For further information about the use of this oscillator for configuration, please see the list of technical documenta-
tion at the end of this data sheet.
Table 2-15. Selectable Master Clock (CCLK) Frequencies During Configuration
Density Shifting
The LatticeECP/EC family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design
targeted for a high-density device to a lower density device. However, the exact details of the final resource utiliza-
tion will impact the likely success in each case.
CCLK (MHz)
10.0
2.5*
4.3
5.4
6.9
8.1
9.2
CCLK (MHz)
2-33
13
15
20
26
30
34
41
CCLK (MHz)
LatticeECP/EC Family Data Sheet
130
45
51
55
60
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Architecture