LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 3

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

SERDES SERDES
sysMEM Embedded Block RAM (EBR)
provides 18kbit dual port RAM.
sysdSP BLOCk diagraM
One LatticeECP2/M device can provide
up to 63,000 Million Multiply Accumu-
lates per second (MMACs)!
Registers
Embedded 3.125Gbps SERDES support
PCI Express, Ethernet (1GbE, SGMII,
CPRI, and OBSAI).
Input
SGMII
Multipliers
1GbE
SERDES SERDES
Registers
Pipeline
OBSAI
CPRI
Accumulator
Subtractor/
Adder/
+ - ∑
+ - ∑
Pre-Engineered
Source Synchronous
Support implements
DDR2 at 533Mbps,
SPI4.2 at 750Mbps
and generic
interfaces up to
840Mbps.
sysDSP Blocks
implement
multipliers, adders,
subtractors,
accumulators.
Configuration
Port supports
SPI, serial and
parallel
configuration.
Summation
+
Registers
Output
Optimized for Low Power
LatticeECP2/M devices are optimized to
offer high functionality and low power.
The static power advantage is achieved by
using various process and architectural
enhancements as well as software power
optimization techniques.
Pre-Engineered Source
Synchronous I/O
The I/O cells in the LatticeECP2/M de-
vices contain a number of pre-engineered
elements to allow the easy implementa-
tion of source synchronous interfaces
such as those found on DDR1/2 memo-
ries, SPI4.2 systems and high-speed
ADC/DACs.
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i/O CELL BLOCk diagraM
Fabric
FPGA
*Based on power calculator results
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Precision DQS/Strobe Delay Control
Dedicated DDR Registers (For Mux
and Demuxing)
Automatic DQS to System Clock
Transfer
2:1 Gearbox Logic to Match I/O Speed
with FPGA Fabric
Low Skew Edge Clocks
ECP2M-20
LatticeECP2M vs. Competition: Static Power
LatticeECP2M: Typical Power Consumption
50K
(Optional)
Static Power (25°C Junction)
Static Power (85°C Junction)
Gearbox
2:1
ECP2M-35 ECP2M-50 ECP2M-70 ECP2M-100
100K
DQS/Strobe Delay &
Transition Detect
LatticeECP2M
150K
Competitor A
LUTs
Output Register
Register Block
Input Register
(2 Flip/Flops)
(2 Flip/Flops)
(5 Flip/Flops)
Tri-State
Block
Block
200K
250K
Competitor X
300K
sysMEM Embedded Block
RAM (EBR)
LatticeECP2/M FPGAs include flexible
sysMEM EBR blocks. sysMEM EBR
blocks provide on-chip memory resourc-
es to support a broad range of features.
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sysCLOCK PLLs & DLLs for
Timing Control
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sysIO Buffer Supports High-
Bandwidth I/O Standards
With Lattice's sysIO interfaces,
LatticeECP2/M devices can easily com-
municate with a variety of devices, sup-
porting many single-ended and differen-
tial I/O standards .
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Up to 5.3Mb sysMEM Embedded
Block RAM (EBR)
3 to 288 Memory Blocks per Device
Configurable Width and Depth
Single Port, Dual Port and
Pseudo Dual Port Modes
Bus Size Matching
RAM Initialization and ROM
Operation
Memory Cascading
PLLs
DLLs
LVCMOS / LVTTL
PCI, LVDS, SSTL, HSTL, Differential
HSTL, Differential SSTL, LVPECL,
BLVDS, RSDS and MLVDS
Eight General Purpose I/O Banks Per
Device
• Frequency Range 2 to 420MHz
• Programmable Input, Scaling,
• Internal and External Feedback
• Frequency Range 100 to 500MHz
• Programmable Phase (11.25 degree
• Optional Duty Cycle Correction
• Additional Matched Delay Block
• Hotsocketing capable
• Programmable slew rate
• Programmable drive strength
• Programmable pull-up, pull-down,
• Programmable open drain
Programmable Phase/Duty Cycle
(22.5 degree steps)
Feedback and Secondary Counters
steps)
bus friendly