LFXP15C-5FN256C Lattice, LFXP15C-5FN256C Datasheet - Page 201
LFXP15C-5FN256C
Manufacturer Part Number
LFXP15C-5FN256C
Description
IC FPGA 15.5KLUTS 188I/O 256-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP15C-5FN256C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 9-40. FIFO with Output Registers, End of Data Read Cycle
And finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle
(as compared to the non-pipelined FIFO), and the RdEn should be high also during that clock cycle, otherwise the
data takes an extra clock cycle when the RdEn goes true.
Figure 9-41. FIFO with Output Registers and RdEn on Output Registers
Almost Full
Almost
Almost
Empty
Empty
Almost
Reset
Clock
WrEn
RdEn
Reset
Empty
Empty
Clock
WrEn
RdEn
Data
Data
Full
Full
Full
Q
Q
Invalid Data
Data_N-5
Data_1
Data_N-4
Data_2
Invalid Data
Data_N-3
9-36
Invalid Data
Data_3
Data_N-2
LatticeECP/EC and LatticeXP Devices
Data_4
Data_N-1
Data_1
Data_5
Memory Usage Guide
Data_N
Data_2
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