LFE3-35EA-6FTN256C Lattice, LFE3-35EA-6FTN256C Datasheet - Page 107
LFE3-35EA-6FTN256C
Manufacturer Part Number
LFE3-35EA-6FTN256C
Description
IC FPGA 35KLUTS 133I/O 256-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-35EA-6FTN256C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-6FTN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LatticeECP3 sysCONFIG Port Timing Specifications (Continued)
Figure 3-20. sysCONFIG Parallel Port Read Cycle
t
Master and Slave SPI (Continued)
t
t
t
t
1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN.
Master Clock Frequency
Duty Cycle
Parameter
CHHH
CHHL
HHCH
HLQZ
HHQX
Parameter
HOLDN Low Hold Time (Relative to CCLK)
HOLDN High Hold Time (Relative to CCLK)
HOLDN High Setup Time (Relative to CCLK)
HOLDN to Output High-Z
HOLDN to Output Low-Z
WRITEN
CCLK
CS1N
BUSY
D[0:7]
*n = last byte of read cycle.
CSN
Selected value - 15%
Over Recommended Operating Conditions
Min.
40
t
t
SUCS
SUWD
Description
Byte 0
t
BSCL
3-54
Byte 1
t
CORD
Selected value + 15%
Max.
t
60
DCB
DC and Switching Characteristics
t
Byte 2
BSCYC
t
BSCH
LatticeECP3 Family Data Sheet
Byte n*
t
t
HCS
HWD
Min.
—
—
5
5
5
Units
MHz
%
Max.
—
—
—
9
9
Units
ns
ns
ns
ns
ns
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