LFXP2-30E-5F672I Lattice, LFXP2-30E-5F672I Datasheet - Page 17
LFXP2-30E-5F672I
Manufacturer Part Number
LFXP2-30E-5F672I
Description
IC FPGA 30KLUTS 472I/O 672-BGA
Manufacturer
Lattice
Datasheet
1.LFXP2-5E-5FTN256C.pdf
(93 pages)
Specifications of LFXP2-30E-5F672I
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Other names
220-1246
Available stocks
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Price
Company:
Part Number:
LFXP2-30E-5F672I
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LATTICE
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Company:
Part Number:
LFXP2-30E-5F672I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Slice Clock Selection
Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing,
can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-13. Slice0 through Slice2 Clock Selection
Figure 2-14. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa-
tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
Secondary Clock
Secondary Clock
Primary Clock
Routing
Routing
Vcc
Vcc
12
12
8
4
1
3
1
2-14
25:1
16:1
Clock to Slice
Slice Control
LatticeXP2 Family Data Sheet
Architecture
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