LFE2M50E-7FN484C Lattice, LFE2M50E-7FN484C Datasheet - Page 31
LFE2M50E-7FN484C
Manufacturer Part Number
LFE2M50E-7FN484C
Description
IC FPGA 50KLUTS 270I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2M50E-7FN484C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Company:
Part Number:
LFE2M50E-7FN484C
Manufacturer:
Lattice Semiconductor Corporation
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Lattice Semiconductor
LatticeECP2/M DSP Performance
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP2/M family.
Table 2-11. DSP Performance
For further information about the sysDSP block, please see the list of additional technical information at the end of
this data sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the
buffer. Table 2-12 provides the PIO signal list.
ECP2M100
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2-6
Device
DSP Block
2-28
18
22
22
24
42
3
6
7
8
6
8
LatticeECP2/M Family Data Sheet
DSP Performance
GMAC
10.4
23.4
28.6
10.4
28.6
31.2
54.6
3.9
7.8
9.1
7.8
Architecture
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