LFE3-95EA-8FN672C Lattice, LFE3-95EA-8FN672C Datasheet - Page 69
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LFE3-95EA-8FN672C
Manufacturer Part Number
LFE3-95EA-8FN672C
Description
IC FPGA 92KLUTS 380I/O 672-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-95EA-8FN672C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-95EA-8FN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
LatticeECP3 External Switching Characteristics
Clocks
Primary Clock
f
t
t
t
f
t
t
t
f
t
t
t
f
t
t
t
Edge Clock
f
t
t
f
t
t
f
t
t
f
t
t
Generic SDR
General I/O Pin Parameters Using Dedicated Clock Input Primary Clock Without PLL
t
t
t
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
CO
SU
H
Parameter
6
6
Frequency for Primary Clock Tree
Clock Pulse Width for Primary Clock ECP3-150EA
Primary Clock Skew Within a Device ECP3-150EA
Primary Clock Skew Within a Bank
Frequency for Primary Clock Tree
Pulse Width for Primary Clock
Primary Clock Skew Within a Device ECP3-70EA/95EA
Primary Clock Skew Within a Bank
Frequency for Primary Clock Tree
Pulse Width for Primary Clock
Primary Clock Skew Within a Device ECP3-35EA
Primary Clock Skew Within a Bank
Frequency for Primary Clock Tree
Pulse Width for Primary Clock
Primary Clock Skew Within a Device ECP3-17EA
Primary Clock Skew Within a Bank
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge of
the Device
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge of
the Device
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge of
the Device
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge of
the Device
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Over Recommended Commercial Operating Conditions
Description
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
3-16
Device
DC and Switching Characteristics
Min. Max. Min. Max. Min. Max.
1, 2
0. 8
0. 8
0. 9
0. 9
0. 9
0.8
0.8
0.9
0.0
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
-8
500
300
250
500
360
310
500
300
250
500
310
220
500
200
500
200
500
200
500
200
3.9
—
—
—
—
—
—
—
—
—
—
2
0.9
0.9
0.9
0.9
1.0
1.0
1.0
1.0
0.0
1.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
420
370
320
210
420
330
280
420
330
280
420
340
230
420
210
420
420
210
420
210
4.3
—
—
—
—
—
—
—
—
—
—
1.0
1.0
1.0
1.0
1.2
1.2
1.2
1.2
0.0
2.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
375
360
300
375
380
330
375
360
300
375
370
240
375
220
375
220
375
220
375
220
4.7
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ps
ps
ns
ps
ps
ns
ps
ps
ns
ps
ps
ns
ps
ns
ps
ns
ps
ns
ps
ns
ns
ns