CY7B933-JCT Cypress Semiconductor Corp, CY7B933-JCT Datasheet - Page 28

• Manufacturer Part Number: CY7B933-JCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7B933-JCT

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02017 Rev. *E
Transmitter Switching Characteristics
Receiver Switching Characteristics
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
15. Transmitter t
16. Data includes D
17. t
18. Loading on RP is the standard TTL test load shown in part (a) of AC Test Loads and Waveforms except C
19. While sending continuous K28.5s, RP unloaded, outputs loaded to 50Ω to V
20. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to CKW input, over the operating
21. The period of t
22. Receiver t
23. Data includes Q
24. t
25. REFCLK has no phase or frequency relationship with CKR and only acts as a centering reference to reduce clock synchronization time. REFCLK must be within
CKW
B
CPWH
CPWL
SD
HD
SENP
HENP
PDR
PPWH
PDF
RISE
FALL
DJ
RJ
RJ
CKR
B
CPRH
CPRL
RH
PRF
PRH
A
ROH
H
CKX
range.
0.1% of the transmitter CKW frequency, necessitating a ±500-PPM crystal.
SENP
A
, t
ROH
and t
, and t
B
HENP
Write Clock Cycle
Bit Time
CKW Pulse Width HIGH
CKW Pulse Width LOW
Data Set-Up Time
Data Hold Time
Enable Set-Up Time (to insure correct RP)
Enable Hold Time (to insure correct RP)
Read Pulse Rise Alignment
Read Pulse HIGH
Read Pulse Fall Alignment
PECL Output Rise Time 20−80% (PECL Test Load)
PECL Output Fall Time 80−20% (PECL Test Load)
Deterministic Jitter (peak-peak)
Random Jitter (peak-peak)
Random Jitter (σ)
is calculated as t
Read Clock Period (No Serial Data Input), REFCLK as
Reference
Bit Time
Read Clock Pulse HIGH
Read Clock Pulse LOW
RDY Hold Time
RDY Pulse Fall to CKR Rise
RDY Pulse Width HIGH
Data Access Time
Data Hold Time
Data Hold Time from CKR Rise
REFCLK Clock Period Referenced to CKW of Trans-
mitter
B
H
is calculated as t
CKR
specifications are only valid if all outputs (CKR, RDY, Q
timing insures correct RP function and correct data load on the rising edge of CKW.
0−7
0−7
will match the period of the transmitter CKW when the receiver is receiving serial data. When data is interrupted, CKR may drift to one of the range limits above.
, SC/D, SVS, ENA, ENN, and BISTEN. t
, SC/D, and RVS.
[25]
[15]
[22]
[21]
CKR
CKW
/10 if no data is being received, or t
[16]
[23, 24]
/10. The byte rate is one tenth of the bit rate.
[13, 20]
[16]
[18]
[23, 24]
Description
Description
[18]
[13, 20]
[18]
[13, 19]
[23, 24]
SD
Over the Operating Range
and t
Over the Operating Range
CKW
HD
[17]
0−7
minimum timing assures correct data load on rising edge of CKW, but not RP function or timing.
/10 if data is being received. See note.
[17]
, SC/D, and RVS) are loaded with similar DC and AC loads.
CC
−2.0V, over the operating range.
[13]
[13]
t
t
5t
5t
5t
4t
2t
2t
Min.
6.25
B
B
–0.1
7B933-155
–1
–2.5
–2.5
B
B
B
B
B
B
–3
–3
–3
–3
–2
–3
6t
4t
6t
Min.
7B923-155
62.5
6.25
[7]
6.5
6.5
B
–4
B
B
5
0
0
2t
+ 8
–3
–3
Max
6.67
+0.1
[7]
+1
B
L
+4
= 15 pF.
Max
66.7
6.67
175
1.2
1.2
35
20
2
t
t
5t
5t
5t
4t
2t
2t
Min.
B
B
–0.1
3.03
–1
–2.5
–2.5
B
B
B
B
B
B
–3
–3
–3
–3
–2
–3
7B933
6t
4t
6t
Min.
30.3
3.03
6.5
6.5
B
–4
B
B
5
0
0
7B923
+ 8
–3
–3
2t
Max.
+0.1
6.25
+1
B
+4
Max
62.5
6.25
175
1.2
1.2
35
20
2
t
t
5t
5t
5t
4t
2t
2t
Min.
B
B
–0.1
2.5
–1
–2.5
–2.5
7B933-400
6t
B
B
B
B
B
B
4t
6t
7B923-400
Min.
–3
–3
–3
–3
–2
–3
2.5
6.5
6.5
B
25
–4
B
B
5
0
0
+ 8
–3
–3
CY7B923
CY7B933
Page 28 of 33
2t
Max.
6.25
+0.1
Max
62.5
6.25
+1
175
1.2
1.2
B
35
20
2
+4
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
[+] Feedback