SAF7118EH/V1/G,518 Trident Microsystems, Inc., SAF7118EH/V1/G,518 Datasheet - Page 22

• Manufacturer Part Number: SAF7118EH/V1/G,518
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAF7118EH/V1/G,518

• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
SAF7118_4
Product data sheet
The increment generation circuit produces the Discrete Time Oscillator (DTO) increment
for both subcarrier generation blocks. It contains a division by the increment of the
line-locked clock generator to create a stable phase-locked sine signal under all conditions
(e.g. for non-standard signals).
The PAL delay line block eliminates crosstalk between the chrominance channels in
accordance with the PAL standard requirements. For NTSC color standards the delay line
can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1.
It is always disabled during VBI or raw data lines programmable by the LCRn registers
(subaddresses 41h to 57h); see
SECAM recombination (cross-over switches).
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•
Loop filter chrominance PLL (only active for PAL/NTSC standards)
PAL/SECAM sequence detection, H / 2-switch generation
Rev. 04 — 4 July 2008
Multistandard video decoder with adaptive comb filter
Section
8.3. The embedded line delay is also used for
SAF7118
© NXP B.V. 2008. All rights reserved.
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