EP1K10TI144-2 Altera, EP1K10TI144-2 Datasheet - Page 24

• Manufacturer Part Number: EP1K10TI144-2
• Manufacturer: Altera

Specifications of EP1K10TI144-2

• Family Name: ACEX™ 1K
• Number Of Usable Gates: 10000
• Number Of Logic Blocks/elements: 576
• # I/os (max): 92
• Frequency (max): 200MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 576
• Ram Bits: 12288
• Device System Gates: 56000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 12. ACEX 1K LE Clear & Preset Modes
24
Asynchronous Load with Clear
Asynchronous Load with Preset
Asynchronous Clear
Chip-Wide Reset
Chip-Wide Reset
(Asynchronous
(Asynchronous
labctrl1 or
(Preset)
labctrl2
labctrl2
labctrl1
labctrl2
(Clear)
labctrl1
(Data)
(Data)
Load)
data3
data3
Load)
NOT
NOT
D
CLRN
VCC
PRN
NOT
NOT
In addition to the six clear and preset modes, ACEX 1K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset.
of how to setup the preset and clear inputs for the desired functionality.
Q
Chip-Wide Reset
Chip-Wide Reset
Asynchronous Preset
labctrl1 or
labctrl2
D
CLRN
PRN
VCC
Q
D
CLRN
(Asynchronous
D
PRN
Asynchronous Load without Clear or Preset
CLRN
PRN
Q
Q
labctrl1
(Data)
Load)
data3
Chip-Wide Reset
Asynchronous Preset & Clear
Chip-Wide Reset
NOT
NOT
labctrl2
labctrl1
Figure 12
Altera Corporation
D
shows examples
CLRN
PRN
Q
D
CLRN
PRN
Q