M28W160CT70N6F Micron Technology Inc, M28W160CT70N6F Datasheet - Page 10

• Manufacturer Part Number: M28W160CT70N6F
• Manufacturer: Micron Technology Inc

Specifications of M28W160CT70N6F

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

M28W160CT, M28W160CB
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
able must be at V
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 9, Read Mode AC Waveforms, and Table
16, Read AC Characteristics, for details of when
the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at V
V
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
Table 3. Bus Operations
Note: X = V
10/50
Bus Read
Bus Write
Output Disable
Standby
Reset
IH
. Commands, Input Data and Addresses are
Operation
IL
or V
IH
, V
PPH
IL
in order to perform a read op-
= 12V ± 5%.
V
V
V
V
E
X
IH
IL
IL
IL
IL
with Output Enable at
V
V
V
G
X
X
IH
IH
IL
V
V
V
W
X
X
IH
IH
IL
RP
V
V
V
V
V
See Figures 10 and 11, Write AC Waveforms, and
Tables 17 and 18, Write AC Characteristics, for
details of the timing requirements.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at V
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable is at V
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V
vice enters Standby mode when finished.
Automatic Standby. Automatic
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity even if Chip Enable is Low, V
current is reduced to I
puts will still output data if a bus Read operation is
in progress.
Reset. During Reset mode when Output Enable
is Low, V
puts are high impedance. The memory is in Reset
mode when Reset is at V
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
able inputs. If Reset is pulled to V
gram or Erase, this operation is aborted and the
memory content is no longer valid.
IH
IH
IH
IH
IL
IH
during a program or erase operation, the de-
IL
WP
, the memory is deselected and the out-
X
X
X
X
X
V
Don't Care
Don't Care
Don't Care
Don't Care
DD
DD1
V
or V
PP
IL
IH
. The data Inputs/Out-
. The power consump-
PPH
and the device is in
IL
SS
, and the supply
Standby
Data Output
during a Pro-
DQ0-DQ15
Data Input
Hi-Z
Hi-Z
Hi-Z
IH
.
pro-