M45PE20-VMN6P Micron Technology Inc, M45PE20-VMN6P Datasheet - Page 30

• Manufacturer Part Number: M45PE20-VMN6P
• Manufacturer: Micron Technology Inc

Specifications of M45PE20-VMN6P

• Cell Type: NOR
• Density: 2Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC N
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256K
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

Instructions
6.11
30/47
Deep power-down (DP)
Executing the deep power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the deep power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all write, program and erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the standby power
mode (if there is no internal cycle currently in progress). But this mode is not the deep
power-down mode. The deep power-down mode can only be entered by executing the deep
power-down (DP) instruction, to reduce the standby current (from I
in
Once the device has entered the deep power-down mode, all instructions are ignored
except the release from deep power-down (RDP) instruction. This releases the device from
this mode.
The deep power-down mode automatically stops at power-down, and the device always
powers-up in the standby power mode.
The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on serial data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of t
to I
Any deep power-down (DP) instruction, while an erase, program or write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 16. Deep power-down (DP) instruction sequence
S
C
D
Table 11: DC
CC2
and the deep power-down mode is entered.
characteristics).
0
1
2
Instruction
3
4
5
6
Figure
7
16.
DP
t
before the supply current is reduced
Standby mode
DP
CC1
Deep power-down mode
to I
CC2
, as specified
M45PE20
AI03753D