DS90CF386MTDX National Semiconductor, DS90CF386MTDX Datasheet - Page 14

• Manufacturer Part Number: DS90CF386MTDX
• Manufacturer: National Semiconductor

Specifications of DS90CF386MTDX

• Lead Free Status / Rohs Status: Not Compliant

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Pin Diagrams for TSSOP Packages
Applications Information
POWER SEQUENCING AND POWERDOWN MODE
Outputs of the transmitter remain in TRI-STATE until the pow-
er supply reaches 2V. Clock and data outputs will begin to
toggle 10 ms after V
pin is above 1.5V. Either device may be placed into a power-
down mode at any time by asserting the Powerdown pin
(active low). Total power dissipation for each device will de-
crease to 5 μW (typical).
The transmitter input clock may be applied prior to powering
up and enabling the transmitter. The transmitter input clock
may also be applied after power up; however, the use of the
PWR DOWN pin is required as described in the Transmitter
Input Clock section. Do not power up and enable (PWR
CC
DS90CF386MTD
has reached 3V and the Powerdown
10108523
14
DOWN = HIGH) the transmitter without a valid clock signal
applied to the TxCLK IN pin.
The FPD Link chipset is designed to protect itself from acci-
dental loss of power to either the transmitter or receiver. If
power to the transmit board is lost, the receiver clocks (input
and output) stop. The data outputs (RxOUT) retain the states
they were in when the clocks stopped. When the receiver
board loses power, the receiver inputs are controlled by a
failsafe bias circuitry. The LVDS inputs are High-Z during ini-
tial power on and power off conditions. Current is limited (5
mA per input) by the fixed current mode drivers, thus avoiding
the potential for latchup when powering the device.
DS90CF366MTD
10108513