MT48LC4M32B2P-7:GTR Micron Technology Inc, MT48LC4M32B2P-7:GTR Datasheet - Page 62

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MT48LC4M32B2P-7:GTR

Manufacturer Part Number
MT48LC4M32B2P-7:GTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC4M32B2P-7:GTR

Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
17/8/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
175mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Figure 46:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
COMMAND
A0–A9, A11
BA0, BA1
DQM0–3
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
BANK 0
T0
ROW
ROW
Alternating Bank Write Accesses
t CKH
t CMH
t AH
t AH
t AH
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
Notes:
t CK
T1
NOP
1. For this example, BL = 4.
2. Faster frequencies require two clocks (when
3. A8, A9, and A11 = “Don’t Care.”
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 3
t DS
BANK 0
WRITE
D
T2
IN
t CMH
t CH
t DH
m
t DS
D
IN
T3
NOP
m + 1
t DH
t DS
D
BANK 1
ACTIVE
IN
ROW
T4
ROW
m + 2
t DH
62
t RCD - BANK 1
t DS
D
IN
T5
NOP
m + 3
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t WR
ENABLE AUTO PRECHARGE
2
- BANK 0
t
COLUMN b 3
t DS
WR >
BANK 1
WRITE
T6
D
IN
t DH
b
t
CK).
t DS
D
NOP
T7
IN
b + 1
t DH
t RP - BANK 0
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
t DS
D
Timing Diagrams
IN
NOP
T8
b + 2
t DH
t DS
D
BANK 0
ACTIVE
T9
IN
ROW
ROW
b + 3
t
t
RCD - BANK 0
WR - BANK 1
DON’T CARE
t DH

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