LMX2352TM National Semiconductor, LMX2352TM Datasheet - Page 14

• Manufacturer Part Number: LMX2352TM
• Description: 07B5847
• Manufacturer: National Semiconductor

Specifications of LMX2352TM

• Pll Type: Frequency Synthesis
• Frequency: 1.2GHz
• Supply Current: 4.75mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 24
• Rohs Compliant: No

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Programming Description
3.2.1 (RF_R [22 - 23] )
1. V2_EN bit when set high enables the voltage doubler for the RF Charge Pump supply.
2. DLL_MODE bit should be set to one for normal usage.
3.2.2 RF_CP_WORD
RF_PD_POL ( RF_R[17] ) should be set to one when RF VCO characteristics are positive. When RF VCO frequency decreases
with increasing control voltage RF_PD_POL should be set to zero.
CP_1x, CP_2x, CP_4x, and CP_8x are used to step the RF Charge Pump output current magnitude from 100 uA to 1.6 mA in
100uA steps as shown in the table below.
RF Charge Pump Output Truth Table
4.0 PROGRAMMABLE DIVIDERS (N COUNTERS)
4.1 IF_N Register
If the Control Bits (CTL [1:0]) are 01, data is transferred from the 24-bit shift register into the IF_N register latch which sets the
PLL 15 bit programmable N counter value and various control functions. The IF_N counter consists of the 3-bit swallow counter
(A counter), and the 12 bit programmable counter (B counter). Serial data format is shown below in tables 4.1.2 and 4.1.3. The
divide ratio (IF_NB_CNTR) must be 3. The divide ratio is programmed using the bits IF_N_CNTR as shown in tables 4.1.2 and
4.1.3. The divide ratio must be 56. The CMOS [3:0] bits program the 2 CMOS outputs detailed in section 4.4.
4.1.1 IF_CTL_WORD
Note: See section 4.2.1.2 for IF control word truth table.
DLL_MODE
MSB
IF_CTL_WORD [2:0]
23
BIT
DLL_MODE
V2_EN
ICPo uA (typ)
CP_8X
1600
100
200
300
400
900
-
-
MSB
IF_CNT_RST
21
LOCATION
RF_R [23]
RF_R [22]
(RF_R[17]-[21])
(IF_R[21]-[23])
V2_EN
CP_4X
CMOS [3:0]
20
RF_R[21]
CP8x
0
0
0
0
1
1
-
-
(Continued)
17
FUNCTION
Delay Line Loop Calibration
Mode
RF_Voltage Doubler Enable
IF_NB_CNTR [11:0]
16
CP_2X
PWDN_IF
RF_R[20]
14
CP4x
0
0
0
0
0
1
-
-
5
CP_1X
IF_NA_CNTR [2:0]
4
RF_R[19]
CP2x
0
0
1
1
0
1
-
-
0
Slow
Disabled
PWDN_MODE
RF_PD_POL
2
LSB
RF_R[18]
CP1x
1
Fast
Enabled
0
1
0
1
0
1
0
1
-
-
LSB
1
0