AD743JN Analog Devices Inc, AD743JN Datasheet - Page 9

• Manufacturer Part Number: AD743JN
• Manufacturer: Analog Devices Inc
• Type: General Purpose Amplifierr

Specifications of AD743JN

• Rail/rail I/o Type: No
• Number Of Elements: 1
• Unity Gain Bandwidth Product: 4.5MHz
• Slew Rate: 2.8V/us
• Common Mode Rejection Ratio: 80dB
• Input Offset Voltage: 1mV
• Input Bias Current: 200pA
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±15V
• Voltage Gain In Db: 132.04dB
• Power Supply Rejection Ratio: 90dB
• Power Supply Requirement: Dual
• Shut Down Feature: No
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): ±4.8V
• Dual Supply Voltage (max): ±18V
• Technology: BiFET
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

HOW CHIP PACKAGE TYPE AND POWER DISSIPATION
AFFECT INPUT BIAS CURRENT
As with all JFET input amplifiers, the input bias current of
the AD743 is a direct function of device junction temperature,
I
tionship between the bias current and the junction temperature
for the AD743. This graph shows that lowering the junction
temperature will dramatically improve I
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 9, where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance ( in °C/W).
From this model, T
mined in a particular application by using Figure 8 together with
the published data for
modify
the Aavid No. 5801.
in chip form. Figure 10 shows the bias current versus the supply
voltage with
predict bias current after
rent will double for every 10°C. The designer using the AD743
in chip form (Figure 11) must also be concerned with both
technology used.
Typically,
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate,
proportionately more of the total
REV. E
B
JC
approximately doubling every 10°C. Figure 8 shows the rela-
Figure 8. Input Bias Current vs. Junction Temperature
and
10
10
10
10
10
10
10
JA
–10
–11
–12
CA
–6
–7
–8
–9
–60
by using of an appropriate clip-on heat sink, such as
, since
JC
P
P
T
T
JC
CA
IN
A
J
JA
IN
will be in the 3°C/W to 5°C/W range; therefore,
Figure 9. Device Thermal Model
= JUNCTION TEMPERATURE
–40
= AMBIENT TEMPERATURE
= DEVICE DISSIPATION
= THERMAL RESISTANCE—JUNCTION TO CASE
= THERMAL RESISTANCE—CASE TO AMBIENT
as the third variable. This graph can be used to
T
J
JC
–20
J
= T
JA
JC
can be affected by the type of die mount
JUNCTION TEMPERATURE ( C)
JA
is also a variable when using the AD743
A
JA
JA
0
and power dissipation. The user can
+
has been computed. Again, bias cur-
CA
20
JA
P
T
V
T
A
IN
S
A
40
JA
= 25 C
= ±15V
. Therefore, I
.
60
B
.
80
JC
will dominate
100
B
can be deter-
120
140
–9–
REDUCED POWER SUPPLY OPERATION FOR LOWER I
Reduced power supply operation lowers I
lowering both the total power dissipation and second, by reduc-
ing the basic gate-to-junction leakage (Figure 10). Figure 12
shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac-coupling capacitor over the –40°C to
+85°C temperature range. If the optional coupling capacitor is
used, this circuit will operate over the entire –55°C to +125°C
military temperature range.
Figure 11. Breakdown of Various Package Thermal
Resistances
Figure 10. Input Bias Current vs. Supply Voltage
for Various Values of
300
200
100
0
5
Figure 12. Piezoelectric Transducer
T
T
A
A
C1*
= +25 C
TRANSDUCER
*OPTIONAL DC BLOCKING CAPACITOR
**OPTIONAL, SEE TEXT
JA
C
= 115 C/W
T
10
CASE
8
100
SUPPLY VOLTAGE ( V)
**
10
T
J
8
JA
A
CT**
10
+
AD743
(DIE MOUNT
TO CASE)
B
10k
(J TO
DIE MOUNT)
B
A
=
+5V
–5V
JA
JC
= 165 C/W
B
in two ways: first, by
JA
AD743
= 0 C/W
15
B