HI-8686PQI Holt Integrated Circuits, HI-8686PQI Datasheet
HI-8686PQI
Specifications of HI-8686PQI
Related parts for HI-8686PQI
HI-8686PQI Summary of contents
Page 1
... TESTB D12 5 24 RESET HI-8685PSI D11 RINB (-10 HI-8685PST D10 7 22 RINA (-10) & ERROR HI-8685PSI-10 D8 PARITY ENB 9 20 HI-8685PST-10 D7 READ HI-8685 28-Pin Plastic SOIC - WB Package RINB- RINB HI-8686PQI 21 - RINA HI-8686PQT 20 - RINA- ERROR 18 - PARITY ENB 17 - N/C HI-8686 32-Pin Plastic PQFP Package RESET 12/08 ...
Page 2
... Parity Enable - A high level activates odd parity checking which replaces the 32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged Error Flag. A high level indicates a bit count error (number of ARINC bits was less than or greater than 32) and/or a parity error if parity detection was enabled ...
Page 3
... The ARINC clock and One/Zero data that are derived from the digital outputs of the built-in line receiver is illustrated in Figure 3. The resulting steam of digital data is shifted into a 32-bit input register. The ARINC clock and One/Zero data can also be created from the TESTA and TESTB inputs as shown in Figure 4. ...
Page 4
... ERROR condition may occur and the first 32 bits of data on the test inputs may not be properly received. Also, when entering the test mode, both TESTA and TESTB should be set high and held in that state for at least one word gap period (17 gap clocks) after high. ...
Page 5
... FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429 TESTA TESTB DERIVED DATA DERIVED CLOCK FIGURE 4 - TEST INPUT TIMING FOR ARINC 429 DERIVED DATA 32nd ARINC bit DATA RDY READ D0 - D15 FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING HI-8685, HI-8686 ARINC Data Bits ARINC Data Bits ...
Page 6
... Supply Voltages V ...................................................+5V CC Temperature Range Industrial ................................ -40°C to +85°C Hi-Temp ............................... -55°C to +125°C Junction Temperature, Tj ................... NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. ...
Page 7
... Vcc = 5V, GND = 0V Operating Temperature Range (unless otherwise specified). PARAMETERS READ pulse width Data delay from READ READ to data floating READ to DATA RDY clear READ pulse to next READ pulse GAPCLK frequency 32nd ARINC bit to DATA RDY HI-8685, HI-8686 SYMBOL TEST CONDITIONS 5. 0. ...
Page 8
... ADDITIONAL HI-8685 PIN CONFIGURATION (See page 1 for additional pin configurations) ORDERING INFORMATION HI - 8685xx For HI-8686PQ please see next page HI-8685, HI-8686 D12 TESTB 5 25 D11 HI-8685PJI RESET 6 24 HI-8685PJT D10 RINB (RINB-10 & D9 RINA (RINA-10 HI-8685PJI-10 D8 ERROR 9 21 HI-8685PJT-10 D7 PARITY ENB ...
Page 9
... ORDERING INFORMATION HI - 8686PQ x x PART NUMBER PART NUMBER PART NUMBER 8686PQ (1) RINA / RINB and RINA-10 / RINB-10 are both available For HI-8685 please see previous page HI-8685, HI-8686 LEAD FINISH Tin / Lead (Sn / Pb) Solder Blank F 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE FLOW ...
Page 10
... REVISION HISTORY Revision Date Description of Change DS8685, Rev. N 12/15/08 Replaced 18-pin SOIC Package Dimension drawing with correct 28-pin drawing, corrected dimensions for PQFP package to reflect current package vendor, and clarified temperature ranges. HI-8685, HI-8686 HOLT INTEGRATED CIRCUITS 10 ...
Page 11
... BSC (1.27) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8685, HI-8686 PACKAGE DIMENSIONS PIN NO. 1 IDENT .045 x 45° .453 ± .003 (11.506 ±.076) SQ. See Detail A .410 ±.020 (10.414 ± ...
Page 12
... BSC SQ (9.00) See Detail A .047 max (1.20) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8685, HI-8686 PACKAGE DIMENSIONS .006 .002 ± (0.152 ± .06) .276 BSC SQ (7.00) .039 .002 ± (1.0 ± .05) .004 .002 ± ...