CY62256VLL-70ZI Cypress Semiconductor Corp, CY62256VLL-70ZI Datasheet - Page 5

CY62256VLL-70ZI

Manufacturer Part Number
CY62256VLL-70ZI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62256VLL-70ZI

Density
256Kb
Access Time (max)
70ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
15b
Package Type
TSOP-I
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
30mA
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Word Size
8b
Number Of Words
32K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62256VLL-70ZI
Manufacturer:
CYPRESS
Quantity:
1 831
Part Number:
CY62256VLL-70ZI
Manufacturer:
CYP
Quantity:
20 000
Document #: 38-05057 Rev. *F
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes:
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of V
8. At any given temperature and voltage condition, t
9. t
I
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
HZOE
/I
OH
, t
and 50 pF load capacitance.
HZCE
[10, 11]
, and t
Parameter
HZWE
are specified with C
Over the Operating Range
L
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
= 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
HZCE
is less than t
LZCE
Description
[8]
[8]
[8, 9]
[8, 9]
[8]
[8, 9]
, t
HZOE
[7]
is less than t
CC
HZWE
/2, input pulse levels of 0 to V
LZOE
and t
, and t
SD
.
HZWE
is less than t
Min.
70
10
10
70
60
60
50
30
10
CY62256V-70
5
0
0
0
0
CC
LZWE
, and output loading of the specified
for any given device.
Max.
70
70
35
25
25
70
25
CY62256V
Page 5 of 12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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