P80C31BH Intel, P80C31BH Datasheet - Page 13

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P80C31BH

Manufacturer Part Number
P80C31BH
Description
Manufacturer
Intel
Datasheet

Specifications of P80C31BH

Cpu Family
MCS51
Device Core
8051
Device Core Size
8b
Frequency (max)
16MHz
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
128Byte
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Through Hole
Pin Count
40
Package Type
PDIP
Lead Free Status / Rohs Status
Not Compliant

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EPROM CHARACTERISTICS
(EPROM Only)
The 87C51 is programmed by a modified Quick-
Pulse Programming algorithm It differs from older
methods in the value used for V
Supply Voltage) and in the width and number of the
ALE PROG pulses
The 87C51 contains two signature bytes that can be
read and used by an EPROM programming system
NOTES
‘‘1’’
‘‘0’’
V
V
(
g
ALE PROG receives 25 programming pulses while V
PP
CC
Read Signature
Program Code Data
Verify Code Data
Pgm Encryption Table
Pgm Lock Bit 1
Pgm Lock Bit 2
10 s) and high for a minimum of 10 s
e
e
e
e
Valid high for that pin
Valid low for that pin
12 75V
5V
MODE
g
20% during programming and verification
g
0 25V
RST
1
1
1
1
1
1
Figure 11 Programming Configuration
PP
Table 3 EPROM Programming Modes
(Programming
PSEN
0
0
0
0
0
0
PP
PROG
ALE
is held at 12 75V Each programming pulse is low for 100
0
0
0
0
1
1
to identify the device The signature bytes identify
the device as an 87C51 manufactured by Intel
Table 3 shows the logic levels for reading the signa-
ture byte and for programming the Program Memo-
ry the Encryption Table and the Lock Bits The cir-
cuit configuration and waveforms for Quick-Pulse
Programming are shown in Figures 11 and 12 Fig-
ure 13 shows the circuit configuration for normal
Program Memory verification
AUTOMOTIVE 80C31BH 80C51BH 87C51
EA
V
V
V
V
V
1
1
PP
PP
PP
PP
PP
P2 7
0
1
0
1
1
1
P2 6
0
0
0
0
1
1
P3 7
0
1
1
1
1
0
270419 –19
P3 6
0
1
1
0
1
0
13
s

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