CY7C344-20PC Cypress Semiconductor Corp, CY7C344-20PC Datasheet - Page 3

• Manufacturer Part Number: CY7C344-20PC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C344-20PC

• Family Name: MAX®
• Memory Type: EPROM
• # Macrocells: 32
• Number Of Usable Gates: 600
• Frequency (max): 71.4MHz
• Propagation Delay Time: 20ns
• Number Of Logic Blocks/elements: 1
• # I/os (max): 16
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03006 Rev. *B
Timing Delays
Timing delays within the CY7C344 may be easily determined
using Warp
software. The CY7C344 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C344 contains circuitry to protect
device pins from high-static voltages or electric fields; however,
normal precautions should be taken to avoid applying any
voltage higher than maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND ≤ (V
inputs must always be tied to an appropriate logic level (either V
GND). Each set of V
directly at the device. Power supply decoupling capacitors of at least
0.2 µF must be connected between V
effective decoupling, each V
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t
When calculating synchronous frequencies, use t
are on the input pins. t
pin. If t
in the data-path mode unless 1/(t
S2
INPUT
I/O
is greater than t
®
, Warp Professional™, or Warp Enterprise™
EXP
CC
I/O DELAY
S2
DELAY
INPUT
to the overall delay.
I/O
and GND pins must be connected together
t
t
IN
IO
CO1
should be used if data is applied at an I/O
CC
, 1/t
pin should be separately decoupled.
WH
S2
becomes the limiting frequency
+ t
IN
WL
CC
or V
) is less than 1/t
and GND. For the most
SYSTEM CLOCK DELAYt
OUT
USE ULTRA37000
) ≤ V
CONTROLDELAY
Figure 1. CY7C344 Timing Model
ALL NEW DESIGNS
LOGIC ARRAY
LOGIC ARRAY
EXPANDER
S1
DELAY
CC
CLOCK
DELAY
DELAY
t
t
t
if all inputs
EXP
S2
LAD
LAC
t
. Unused
IC
.
CC
or
t
t
t
t
CLR
PRE
RSU
RH
ICS
FEEDBACK
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
1/(t
lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
t
an I/O pin, t
t
frequency in the data-path mode unless 1/(t
1/(t
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
of 1/(t
The lowest of these frequencies is the maximum data-path frequency
for the asynchronous configuration.
The parameter t
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous clock. If t
than the minimum required input hold time of the subsequent
synchronous logic, then the devices are guaranteed to function
properly with a common synchronous clock under worst-case
environmental and supply voltage conditions.
The parameter t
device when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344. In general, if t
is greater than the minimum required input hold time of the subse-
quent logic (synchronous or asynchronous), then the devices are
guaranteed to function properly under worst-case environmental and
supply voltage conditions, provided the clock signal source is the
same. This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This is due to
the expander logic in the second device’s clock signal path adding an
additional delay (t
device to change prior to the arrival of the clock signal at the following
device’s register.
AH
AS1
DELAY
WH
AS2
) is greater than t
t
FD
if all inputs are on dedicated input pins. If any data is applied to
AWH
TM
+ t
+ t
REGISTER
WL
AH
+ t
t
t
LATCH
FOR
COMB
AS2
t
RD
), 1/t
).
AWL
must be used as the required set-up time. If (t
), 1/t
CO1
OH
EXP
AOH
ACO1
indicates the system compatibility of this device
, or 1/(t
), causing the output data from the preceding
ACO1
indicates the system compatibility of this
, or 1/(t
, 1/(t
EXP
OUTPUT
DELAY
AS2
+ t
EXP
t
t
t
OD
XZ
ZX
S1
EXP
+ t
EXP
+ t
) is the lowest frequency. The
AS1
AH
to t
to t
AWH
) is the lowest frequency.
) becomes the limiting
S1
AS1
. Determine which of
+ t
CY7C344
OUTPUT
. Determine which
AWL
Page 3 of 15
OH
) is less than
is greater
AS2
AOH
+