MC14568BCP ON Semiconductor, MC14568BCP Datasheet - Page 7

• Manufacturer Part Number: MC14568BCP
• Manufacturer: ON Semiconductor

Specifications of MC14568BCP

• Operating Temperature (max): 125C
• Package Type: PDIP
• Pin Count: 16
• Mounting: Through Hole
• Lead Free Status / Rohs Status: Not Compliant

divider ( 4,
by–N 4–bit counter.
PHASE COMPARATOR
circuit. It essentially consists of four flip–flops and an output
pair of MOS transistors. Only one of its inputs (PC in , pin 14)
is accessible externally. The second is connected to the out-
put of one of the two counters D1 or D2 (see block diagram).
taken into consideration since the comparator responds to
leading edges only.
phases, with signal A (pin 14) leading signal B (Ref.), the
comparator output will be high for the time equal to the
phased difference.
time. In between, the output will be in a three–state condition
and the voltage on the capacitor of an RC filter normally con-
nected at this point will have some intermediate value (see
Figure 4). When used in a phase locked loop, this value will
adjust the Voltage Controlled Oscillator frequency by reduc-
ing the phase difference between the reference signal and
the divided VCO frequency to zero.
MOTOROLA CMOS LOGIC DATA
The MC14568B contains a phase comparator, a fixed
The phase comparator is a positive edge controlled logic
Duty cycles of both input signals (at A and B) need not be
If both input signals have identical frequencies but different
If signal A lags signal B, the output will be low for the same
A (PC in )
B (REF.)
Figure 4. Phase Comparator Waveforms
PC out
LD
16,
64,
100) and a programmable divide–
(LOCK DETECT)
INPUT STATE
1/f
A
PC out
X X
LD
B
Figure 5. Phase Comparator State Diagram
OPERATING CHARACTERISTICS
01
V DD
V SS
V OH
V OL
V OH
V OL
V OH
V OL
00
11
0
0
10
OUTPUT DISCONNECTED
10
signal will be high when signal B has a lower frequency than
signal A, and low otherwise.
output will vary between V OH (or V OL ) and some intermedi-
ate value until the frequencies of both signals are equal and
their phase difference equal to zero, i.e. until locked condition
is obtained.
quency range. The comparator is provided with a lock indi-
cator output, which will stay at logic 1 in locked conditions.
transitions. It assumes that only one transition on either sig-
nal occurs at any time. It shows that a change of the output
state is always associated with a positive transition of either
signal. For a negative transition, the output does not change
state. A positive transition may not cause the output to
change, this happens when the signals have different fre-
quencies.
DIVIDE BY 4, 16, 64 OR 100 COUNTER (D1)
for a V DD value of 10 volts over the standard temperature
range when dividing by 4, 64 and 100. Programming is ac-
complished by use of inputs F and G (pins 10 and 11) ac-
cording to the truth table shown. Connecting the Control
input (CTL, pin 15), to V DD allows cascading this counter with
the programmable divide–by–N counter provided in the
same package. Independent operation is obtained when the
Control input is connected to V SS .
the reference frequencies corresponding to the channel
spacings normally required in frequency synthesizer applica-
tions. For example. with the division ratio 100 and a 5 MHz
crystal stabilized source a reference frequency of 50 kHz is
supplied to the comparator. The lower division ratios permit
operation with low frequency crystals.
If the input signals have different frequencies, the output
Under the same conditions of frequency difference, the
Capture and lock range will be determined by the VCO fre-
The state diagram (Figure 5) depicts the internal state
This counter is able to work at an input frequency of 5 MHz
The different division ratios have been chosen to generate
3–STATE
00
11
1
01
01
00
11
1
0
10
MC14568B
7