CY7C128A-45PC Cypress Semiconductor Corp, CY7C128A-45PC Datasheet

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CY7C128A-45PC

Manufacturer Part Number
CY7C128A-45PC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C128A-45PC

Density
16Kb
Access Time (max)
45ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
11b
Package Type
PDIP
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
120mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
24
Word Size
8b
Number Of Words
2K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C128A-45PC
Manufacturer:
ATMEL
Quantity:
2 889
Part Number:
CY7C128A-45PC
Quantity:
200
Part Number:
CY7C128A-45PC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Features
Cypress Semiconductor Corporation
Document #: 38-05028 Rev. *B
Automatic power-down when deselected
CMOS for optimum speed/power
High speed
Low active power
Low standby power
TTL-compatible inputs and outputs
Capable of withstanding greater than 2001V electrostatic
discharge
Available in Pb-free 24-pin Molded SOJ, non Pb-free 24-pin
(300-Mil) Molded DIP
20 ns
660 mW (commercial)
110 mW (20 ns)
Logic Block Diagram
CE
WE
OE
A
A
A
A
A
A
A
10
9
8
7
6
5
4
A
3
INPUT BUFFER
128 x 16 x 8
DECODER
COLUMN
ARRAY
A
2
198 Champion Court
A
1
A
0
POWER
DOWN
Functional Description
The CY7C128A is a high-performance CMOS static RAM
organized as 2048 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), and active LOW
Output Enable (OE) and tri-state drivers. The CY7C128A has an
automatic power-down feature, reducing the power consumption
by 83% when deselected.
Writing to the device is accomplished when the Chip Enable (CE)
and Write Enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O
memory location specified on the address pins (A
Reading the device is accomplished by taking Chip Enable (CE)
and Output Enable (OE) LOW while Write Enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the eight
I/O pins.
The I/O pins remain in high-impedance state when Chip Enable
(CE) or Output Enable (OE) is HIGH or Write Enable (WE) is
LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
San Jose
C128A–1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
,
0
1
2
3
4
5
6
7
CA 95134-1709
2K x 8 Static RAM
0
through I/O
Revised March 19, 2010
7
) is written into the
CY7C128A
0
408-943-2600
through A
10
).
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Related parts for CY7C128A-45PC

CY7C128A-45PC Summary of contents

Page 1

... I/O pins. The I/O pins remain in high-impedance state when Chip Enable (CE) or Output Enable (OE) is HIGH or Write Enable (WE) is LOW. The CY7C128A utilizes a die coat to insure alpha immunity. INPUT BUFFER 128 ARRAY POWER ...

Page 2

... Selection Guide Description Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Pin Configuration Document #: 38-05028 Rev. *B -20 - 120 120 20 20 Figure 1. 24-Pin DIP/SOJ (Top View 7C128A I I/O I I/O I I GND 13 I/O 3 CY7C128A Page [+] Feedback ...

Page 3

... I CC GND < V < V – Output Disabled V = Max OUT Max > IH, Min. Duty Cycle = 100% Max >V –0.3V > V –0. < 0.3V IN CY7C128A Ambient Temperature V CC   5V  10 +70 C -20 -45 Max. Min. Max. Unit 2.4 V 0 0.8 –0.5 0.8 V A +10 – ...

Page 4

... JIG AND Equivalent to: (b) SCOPE C128A–4 [2, 5] -20 Min less than t for any given device. HZCE LZCE CY7C128A Max. Unit ALL INPUT PULSES 90% 90% 10% 10%  C128A–5 THÉ VENIN EQUIVALENT 167 OUTPUT 1.73V -45 Max. Min. Max. Unit ...

Page 5

... IL 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05028 Rev OHA DOE DATA VALID 50% [ SCE PWE t SD DATA VALID IN t HZWE . CY7C128A DATA VALID C128A–6 t HZOE t HZCE HIGH IMPEDANCE 50 C128A– LZWE HIGH IMPEDANCE C128A–8 Page [+] Feedback ...

Page 6

... Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write. 13 goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05028 Rev. *B [8, 12, 13 SCE PWE t SD DATA VALID IN t HZWE CY7C128A HIGH IMPEDANCE C128A–9 Page [+] Feedback ...

Page 7

... SUPPLY VOLTAGE(V) Ordering Information Speed (ns) Ordering Code 20 CY7C128A-20VXC 45 CY7C128A-45PC Please contact local sales representative regarding availability of these parts Document #: 38-05028 Rev. *B NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 1 0.8 0 5.0V IN ...

Page 8

... Package Diagrams Document #: 38-05028 Rev. *B Figure 2. 24-pin (300-Mil) Molded DIP (51-85013) Figure 3. 24-pin (300-Mil) SOJ (51-85030) CY7C128A 51-85013 *C 51-85030 *C Page [+] Feedback ...

Page 9

... Document History Page Document Title: CY7C128A Static RAM Document Number: 38-05028 Orig. of REV. ECN NO. Issue Date Change ** 106814 09/10/01 *A 493543 See ECN *B 2892244 03/19/2010 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office ...

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