IS62C1024-70T ISSI, Integrated Silicon Solution Inc, IS62C1024-70T Datasheet
IS62C1024-70T
Specifications of IS62C1024-70T
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IS62C1024-70T Summary of contents
Page 1
... CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C1024 is available in 32-pin plastic SOP and TSOP (type 1) packages. DECODER MEMORY ARRAY I/O ...
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... IS62C1024 PIN CONFIGURATION 32-Pin SOP VCC A16 2 31 A15 A14 3 30 CE2 A12 A13 ISSI 62C1024 A11 A10 CE1 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 16 17 I/O3 PIN DESCRIPTIONS A0-A16 Address Inputs CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input OE Output Enable Input ...
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... IS62C1024 TRUTH TABLE E CE1 Mode CE2 Not Selected X H (Power-down Output Disabled H L Read H L Write L L ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT Notes: 1 ...
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... IS62C1024 POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions = Max Vcc Dynamic Operating Supply Current mA OUT I TTL Standby Current V = Max (TTL Inputs CE2 V I CMOS Standby V = Max CE1 V Current (CMOS Inputs) CE2 0.2V Notes address and data inputs are cycling at the maximum frequency means no input lines change. ...
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... IS62C1024 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE1 Access Time t 1 ACE t CE2 Access Time 2 ACE OE Access Time t DOE OE to Low-Z Output t (2) LZOE OE to High-Z Output t (2) HZOE ...
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... IS62C1024 (1,3) READ CYCLE NO. 2 ADDRESS OE CE1 CE2 DOUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = V 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time ...
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... IS62C1024 AC WAVEFORMS WE WRITE CYCLE NO Controlled) ADDRESS CE1 CE2 WE DOUT DIN E1 WRITE CYCLE NO CE2 Controlled) ADDRESS CE1 CE2 WE DOUT DIN Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write ...
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... TSOP, Type 1 55 IS62C1024-55QI Plastic SOP 55 IS62C1024-55TI TSOP, Type 1 70 IS62C1024-70QI Plastic SOP 70 IS62C1024-70TI TSOP, Type 1 Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ISSI Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com ® ...