AT49F080-90TC Atmel, AT49F080-90TC Datasheet - Page 2

• Manufacturer Part Number: AT49F080-90TC
• Manufacturer: Atmel

Specifications of AT49F080-90TC

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

To allow for simple in-system reprogrammability, the
AT49F080(T) does not require high input voltages for pro-
gramming. 5-volt-only commands determine the read and
programming operation of the device. Reading data out of
the device is similar to reading from an EPROM. Repro-
gramming the AT49F080(T) is performed by erasing the
entire 8 megabits of memory and then programming on a
byte-by-byte basis. The typical byte programming time is a
fast 10 s. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a
Block Diagram
Device Operation
READ: The AT49F080(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention.
ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
2
ADDRESS
INPUTS
GND
VCC
WE
OE
CE
EC
. If the boot block lockout feature has
AT49F080(T)
OE, CE, AND WE
Y DECODER
X DECODER
LOGIC
DATA INPUTS/OUTPUTS
BLOCK (16K BYTES)
OPTIONAL BOOT
INPUT/OUTPUT
MAIN MEMORY
(1008K BYTES)
DATA LATCH
Y-GATING
I/O7 - I/O0
BUFFERS
AT49F080
byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
8
FFFFFH
04000H
03FFFH
00000H
DATA INPUTS/OUTPUTS
BLOCK (16K BYTES)
OPTIONAL BOOT
INPUT/OUTPUT
MAIN MEMORY
(1008K BYTES)
DATA LATCH
Y-GATING
I/O7 - I/O0
BUFFERS
AT49F080T
8
FFFFFH
FC000H
FBFFFH
00000H
BP
cycle