LH28F160BJE-TTL90 Sharp Electronics, LH28F160BJE-TTL90 Datasheet
LH28F160BJE-TTL90
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LH28F160BJE-TTL90 Summary of contents
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... Flash Memory LH28F160BJE-TTL90 Date Mar. 16. 2000 ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 1.3 Product Description...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization................................................. 4 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 8 3.1 Read.............................................................................. ...
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... Top Boot Location Extended Cycling Capability Minimum 100,000 Block Erase Cycles SHARP’s LH28F160BJE-TTL90 Flash memory is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F160BJE-TTL90 can operate at V capability realize battery life and suits for cellular phone application. ...
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... GND is recommended for designs that switch V off during read operation. CCW 1.2 Product Overview The LH28F160BJE-TTL90 is a high-performance 16M-bit Boot Block Flash memory organized as 1M-word of 16 bits or 2M-byte of 8 bits. The 1M-word/2M-byte of data is arranged in two 4K-word/8K-byte boot blocks, six 4K- word/8K-byte parameter blocks and thirty-one 32K- word/64K-byte main blocks which are individually erasable, lockable and unlockable in-system ...
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... For example, changing data from "10111101" to "10111100" requires "11111110" programming. 1.3 Product Description supply voltage CC 1.3.1 Package Pinout LH28F160BJE-TTL90 Boot Block Flash memory is available in 48-lead TSOP package (see Figure 2). CCR 1.3.2 Block Organization , the I CMOS CC This product architecture providing system memory integration ...
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Output Buffer Y Input A -A Decoder -1 19 Buffer Address X Decoder Latch Address Counter Figure 1. Block Diagram ...
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... CCW may be connected to 12V±0.3V for a total of 80 hours maximum. DEVICE POWER SUPPLY: Do not float any power pins. With V V SUPPLY the flash memory are inhibited. Device operations at invalid V CC Characteristics) produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. ...
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... PRINCIPLES OF OPERATION The LH28F160BJE-TTL90 flash memory includes an on- chip WSM to manage block erase, full chip erase, word/byte write and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal processor overhead with RAM-like interface timings ...
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... Refer to Table 5 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes ...
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Read Identifier Codes The read identifier codes operation manufacturer code, device code, block lock configuration codes for each block and the permanent lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically ...
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Mode Notes Read 8 Output Disable Standby Reset 4 Read Identifier Codes 8 Write 6,7,8 Mode Notes Read 8 Output Disable Standby Reset 4 Read Identifier Codes 8 Write 6,7,8 NOTES: 1. Refer to DC Characteristics. When ...
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Bus Cycles Command Req’d. Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Full Chip Erase Word/Byte Write Block Erase and Word/Byte Write Suspend Block Erase and Word/Byte Write Resume Set Block Lock-Bit Clear Block Lock-Bits ...
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Read Array Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another ...
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Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to V ...
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Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and WP# pin. The block lock-bits and WP# pin gates program and erase operations while ...
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... Block Locking by the WP# This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. The lockable two boot blocks are locked when WP#=V any program or erase operation to a locked block will ...
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WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above Range ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H Write Word/Byte Data and Address Read Status Register Suspend Word/Byte No Suspend 0 SR.7= Word/Byte Yes Write 1 Full Status Check if Desired Word/Byte Write Complete FULL ...
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Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Word/Byte Write Read Word/Byte Write ? Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Write FFH Read Array Data Block ...
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Start Write B0H Read Status Register 0 SR. Word/Byte Write Completed SR.2= 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word/Byte Write Resumed Read Array Data Figure 9. Word/Byte Write Suspend/Resume Flowchart ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V ...
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... PC board trace inductance. 5.4 V Trace on Printed Circuit Boards CCW Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V CCW supplies the memory cell current for word/byte writing and block erasing ...
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... For the lockout voltage, refer to the specification. (See chapter 6.2.3.) 3) Data protection through RP# When the RP# is kept low during read mode, the flash memory will be reset mode, then write protecting all blocks. When the RP# is kept low during power up and ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration ................0°C to +70°C Storage Temperature During under Bias ............................... -10°C to +80°C During non Bias ................................ -65°C to +125°C ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...
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DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Auto Power-Save Current CCAS Reset Power-Down Current CCD Read Current CCR ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout during Normal CCWLK CCW Operations V V during ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV V ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) ...
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AC CHARACTERISTICS - WRITE OPERATIONS Sym. t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP#V Setup to WE# Going ...
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V IH ADDRESSES( CE#( ELWL V IH OE#( WE#( High Z DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR.7) V ...
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ALTERNATIVE CE#-CONTROLLED WRITES Sym. t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP#V Setup to CE# Going High SHEH ...
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V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR. ...
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RESET OPERATIONS High Z ("1") RY/BY#(R) (SR. ("0" RP#( High Z ("1") RY/BY#(R) (SR. ("0" RP#( (B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit ...
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BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter t Word Write Time WHQV1 t EHQV1 Byte Write Time Block Write Time (In word mode) Block Write Time (In byte mode) t WHQV2 Block Erase ...
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ADDITIONAL INFORMATION 1 Block Erase Suspend and Resume command If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than 15ms and both commands are written repeatedly, a longer time is ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...