LH28F320BJE-PTTL90 Sharp Electronics, LH28F320BJE-PTTL90 Datasheet - Page 10

• Manufacturer Part Number: LH28F320BJE-PTTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F320BJE-PTTL90

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

2 PRINCIPLES OF OPERATION
The LH28F320BJE-PTTL90 flash memory includes an
on-chip WSM to manage block erase, full chip erase,
word/byte write and lock-bit configuration functions. It
allows for: fixed power supplies during block erase, full
chip erase, word/byte write and lock-bit configuration, and
minimal processor overhead with RAM-like interface
timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contents−block
erase,
configuration, status and identifier codes−are accessed via
the CUI and verified through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
full
CCW
chip
enables successful block erase, full chip
erase,
word/byte
CCW
write,
voltage. High
lock-bit
Interface software that initiates and polls progress of block
erase, full chip erase, word/byte write and lock-bit
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.
2.1 Data Protection
When V
altered. The CUI, with two-step block erase, full chip
erase, word/byte write or lock-bit configuration command
sequences, provides protection from unwanted operations
even when high voltage is applied to V
functions are disabled when V
lockout voltage V
block locking capability provides additional protection
from inadvertent code or data alteration by gating block
erase, full chip erase and word/byte write operations.
Refer to Table 5 for write protection alternatives.
CCW
V
CCWLK
LKO
or when RP# is at V
, memory contents cannot be
CC
is below the write
CCW
IL
. The device’s
. All write
Rev. 1.27