LH28F320BJHE-PTTL90 Sharp Electronics, LH28F320BJHE-PTTL90 Datasheet - Page 19

• Manufacturer Part Number: LH28F320BJHE-PTTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F320BJHE-PTTL90

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

4.12 OTP Program Command
OTP program is executed by a two-cycle command
sequence. OTP program command(C0H) is written,
followed by a second write cycle that specifies the address
and data (latched on the rising edge of WE#). The WSM
then takes over, controlling the OTP program and program
verify algorithms internally. After the OTP program
command sequence is completed, the device automatically
outputs status register data when read (see Figure 13). The
CPU can detect the completion of the OTP program by
analyzing the output data of the RY/BY# pin or status
register bit SR.7.
When OTP program is completed, status register bit SR.4
should be checked. If OTP program error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully
program to "0"s. The CUI remains in read status register
mode until it receives other commands.
Reliable OTP program can be executed only when
V
this voltage, memory contents are protected against OTP
sharp
Block Erase ≤V
Clear Block ≤V
CC
Word/Byte
Permanent
Operation
Lock-Bits
Set Block
Full Chip
Lock-Bit
Lock-Bit
=2.7V-3.6V and V
Write
Erase
Set
or
>V
≤V
>V
≤V
>V
>V
≤V
>V
V
CCWLK
CCWLK
CCWLK
CCWLK
CCWLK
CCWLK
CCWLK
CCWLK
CCWLK
CCWLK
CCW
CCW
=V
RP#
V
V
V
V
V
V
V
V
V
V
X
X
X
X
X
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
CCWH1/2
Permanent
Lock-Bit
. In the absence of
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
Table 5. Write Protection Alternatives
Lock-bit
Block
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
LHF32J04
WP#
V
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IL
IH
IL
IH
IL
IH
All Blocks Locked.
All Blocks Locked.
2 Boot Blocks Locked.
Block Erase and Word/Byte Write Enabled.
Block Erase and Word/Byte Write Disabled.
Block Erase and Word/Byte Write Disabled.
All Blocks Locked.
All Blocks Locked.
All Unlocked Blocks are Erased.
2 Boot Blocks and Locked Blocks are NOT Erased.
All Unlocked Blocks are Erased,
Locked Blocks are NOT Erased.
Set Block Lock-Bit Disabled.
Set Block Lock-Bit Disabled.
Set Block Lock-Bit Enabled.
Set Block Lock-Bit Disabled.
Clear Block Lock-Bits Disabled.
Clear Block Lock-Bits Disabled.
Clear Block Lock-Bits Enabled.
Clear Block Lock-Bits Disabled.
Set Permanent Lock-Bit Disabled.
Set Permanent Lock-Bit Disabled.
Set Permanent Lock-Bit Enabled.
programs.
V
to "1". If OTP write is attempted when the OTP Lock-bit
is set, SR.1 and SR.4 is set to "1".
4.13 Block Locking by the WP#
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
The lockable two boot blocks are locked when WP#=V
any program or erase operation to a locked block will
result in an error, which will be reflected in the status
register. For top configuration, the top two boot blocks are
lockable. For the bottom configuration, the bottom two
boot blocks are lockable. If WP# is V
bit is not set, boot block can be programmed or erased
normally (Unless V
only two boot blocks, other blocks are not affected.
CCW
≤V
CCWLK
If
, status register bits SR.3 and SR.4 is set
OTP
CCW
program
Effect
is below V
is
CCWLK
IH
attempted
and block lock-
). WP# is valid
Rev. 1.27
while
17
IL
;