PA28F400BVB60 Intel, PA28F400BVB60 Datasheet - Page 12
PA28F400BVB60
Manufacturer Part Number
PA28F400BVB60
Description
Manufacturer
Intel
Datasheet
1.PA28F400BVB60.pdf
(57 pages)
Specifications of PA28F400BVB60
Density
4Mb
Access Time (max)
60ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
19/18Bit
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
0C to 70C
Package Type
SOP
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
3/4.5V
Operating Supply Voltage (max)
3.6/5.5V
Word Size
8/16Bit
Number Of Words
512K/256K
Supply Current
65mA
Mounting
Surface Mount
Pin Count
44
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PA28F400BVB60
Manufacturer:
INTEL
Quantity:
45
Part Number:
PA28F400BVB60
Manufacturer:
INTEL
Quantity:
20 000
4-MBIT SmartVoltage BOOT BLOCK FAMILY
12
WP#
BYTE#
V
V
GND
NC
CC
PP
Symbol
INPUT
INPUT
Type
WRITE PROTECT: Provides a method for unlocking the boot block in a system
without a 12 V supply.
When WP# is at logic low, the boot block is locked, preventing program and
erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the status register to indicate the operation
failed.
When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.
NOTE: This feature is overridden and the boot block unlocked when RP# is at
V
BYTE# ENABLE: Not available on 28F004B. Controls whether the device
operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin
must be controlled at CMOS levels to meet the CMOS current specification in the
standby mode.
When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ
address that decodes between the upper and lower byte. DQ
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is
read and programmed on DQ
DEVICE POWER SUPPLY: 5.0 V
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5 V
be applied to this pin. When V
against Program and Erase commands.
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
HH
Table 2. 28F400/004 Pin Descriptions (Continued)
. See Section 3.4 for details on write protection.
SEE NEW DESIGN RECOMMENDATIONS
0
0
PP
–DQ
–DQ
Name and Function
< V
7
15
PPLK
and DQ
10%, 3.3
.
all blocks are locked and protected
15
/A
0.3 V, 2.7 V–3.6 V (BE/CE only)
–1
becomes the lowest order
10% or 12 V
8
–DQ
14
are tri-stated
5% must