TB28F400BVT80 Intel, TB28F400BVT80 Datasheet - Page 6

• Manufacturer Part Number: TB28F400BVT80
• Manufacturer: Intel

Specifications of TB28F400BVT80

• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

4-MBIT SmartVoltage BOOT BLOCK FAMILY
For program and erase operations, 5 V V
operation eliminates the need for in system voltage
converters, while 12 V V
faster program and erase for situations where 12 V
is available, such as manufacturing or designs
where 12 V is in-system. For design simplicity,
however, just hook up V
± 10% source.
The 28F400/28F004B boot block flash memory
family is a high-performance, 4-Mbit (4,194,304 bit)
flash
256 Kwords of 16 bits each (28F400 only) or
512 Kbytes of 8 bits each (28F400 and 28F004B).
Separately erasable blocks, including a hardware-
lockable boot block (16,384 bytes), two parameter
blocks (8,192 bytes each) and main blocks (one
block of 98,304 bytes and three blocks of 131,072
bytes),
architecture. See Figures 7 and 8 for memory
maps. Each block can be independently erased and
programmed
temperature
temperature.
The boot block is located at either the top (denoted
by -T suffix) or the bottom (-B suffix) of the address
map
microprocessor protocols for boot code location.
The
complete code security for the kernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.4 for details).
The Command User Interface (CUI) serves as the
interface
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and
thereby
microcontroller of these tasks. The Status Register
(SR) indicates the status of the WSM and whether it
successfully completed the desired program or
erase operation.
Program and Erase Automation allows program and
erase operations to be executed using an industry-
standard two-write command sequence to the CUI.
Data writes are performed in word (28F400 family)
or byte (28F400 or 28F004B families) increments.
6
erase
hardware-lockable
in
memory
define
unburdening
between
order
operations,
or
100,000
the
family
10,000
to
boot
CC
the
the
accommodate
times
and V
organized
boot
including
PP
times
block
microprocessor
microprocessor
operation provides
PP
block
at
to the same 5 V
at
flash
verifications,
commercial
SEE NEW DESIGN RECOMMENDATIONS
as
extended
provides
different
family
either
PP
or
or
Each byte or word in the flash memory can be
programmed
locations, unlike erases, which erase all locations
within a block simultaneously.
The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by
turning most of the flash memory’s circuitry off. This
mode is controlled by the RP# pin and its usage is
discussed in Section 3.5, along with other power
consumption issues.
Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences. For
example, when the flash memory powers-up, it
automatically defaults to the read array mode, but
during a warm system reset, where power
continues uninterrupted to the system components,
the flash memory could remain in a non-read mode,
such as erase. Consequently, the system Reset
signal should be tied to RP# to reset the memory to
normal read mode upon activation of the Reset
signal. See Section 3.6.
The 28F400 provides both byte-wide or word-wide
input/output, which is controlled by the BYTE# pin.
Please see Table 2 and Figure 16 for a detailed
description of BYTE# operations, especially the
usage of the DQ
The
ROM/EPROM-compatible pinout and housed in the
44-lead PSOP (Plastic Small Outline) package, the
48-lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-lead TSOP as shown in
Figures 4, 5 and 6, respectively. The 28F004
products are available in the 40-lead TSOP
package as shown in Figure 3.
Refer to the DC Characteristics , Section 4.4
(commercial
(extended temperature), for complete current and
voltage
Characteristics ,
temperature)
temperature), for read, write and erase performance
specifications.
28F400
specifications.
independently
temperature)
and
15
products
/A
Section
–1
pin.
Section
Refer
are
and
of
4.5
4.12
available
other
to
Section
(commercial
(extended
the
memory
in
4.11
AC
a