PA28F004SC-85 Intel, PA28F004SC-85 Datasheet - Page 37

• Manufacturer Part Number: PA28F004SC-85
• Manufacturer: Intel

Specifications of PA28F004SC-85

• Density: 4Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

6.6
T
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
A
W10 t
W11 t
W12 t
W13 t
W14 t
W15 t
W1
W2
W3
W4
W5
W6
W7
W8
W9
= 0°C to +70°C
PRELIMINARY
#
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
A write operation can be initiated and terminated with either CE# or WE#.
Sampled, not 100% tested.
Refer to Table 4 for valid A
V
or lock-bit configuration success (SR.1/3/4/5 = 0).
See Ordering Information for device speeds (valid operational combinations).
Write pulse width (t
(whichever goes high first). Hence, t
WE# pulse width requirement decreases to t
Block erase, program, and lock-bit configuration with V
Write pulse width high (t
(whichever goes low last). Hence, t
PP
should be held at V
t
t
t
t
t
t
t
t
t
PHWL
ELWL
WP
DVWH
AVWH
WHEH
WHDX
WHAX
WPH
PHHWH
VPWH
WHGL
WHRL
QVPH
QVVL
AC Characteristics—Write Operations
(t
Sym
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
PHEL
AVEH
EHAX
(t
VPEH
EHRL
DVEH
EHWH
EHDX
EHGL
PHHEH
)
)
)
WP
)
)
)
)
)
)
)
) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
) RP# V
PPH1/2/3
WPH
Versions
RP# High Recovery to WE# (CE#) Going
Low
CE# (WE#) Setup to WE# (CE#) Going
Low
Write Pulse Width
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
Write Pulse Width High
V
Write Recovery before Read
WE# (CE#) High to RY/BY# Going Low
RP# V
High
V
IN
PP
PP
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
and D
Setup to WE# (CE#) Going High
Hold from Valid SRD, RY/BY# High
(and if necessary RP# should be held at V
HH
HH
IN
WPH
WP
Setup to WE# (CE#) Going High
Hold from Valid SRD, RY/BY#
for block erase, program, or lock-bit configuration.
= t
= t
WLWH
WHWL
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
Parameter
WP
– 10 ns for 5 V V
= t
= t
ELEH
EHEL
CC
= t
= t
WLEH
WHEL
3.0 V should not be attempted.
= t
= t
2.7 V 3.6 V V
CC
(1,2)
5 V ± 10% V
3.3 V ± 0.3 V,
ELWH
EHWL
and t
5 V ± 5%,
—Commercial Temperature
. If CE# is driven low 10 ns before WE# going low,
.
WP
HH
– 20 ns for 2.7 V and 3.3 V V
Notes Min
) until determination of block erase, program,
3,5,8
3,5,8
3,8
3,8
3
7
7
4
4
9
8
CC
CC
Valid for All
100
100
50
40
40
25
Speeds
1
0
0
5
5
0
0
0
Max
90
Valid for All
Min
100
100
70
50
50
25
1
0
0
5
5
0
0
0
Speeds
CC
writes.
Max
90
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
37