PA28F016SC-95 Intel, PA28F016SC-95 Datasheet - Page 18

• Manufacturer Part Number: PA28F016SC-95
• Manufacturer: Intel

Specifications of PA28F016SC-95

• Density: 16Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also,
reliable block erasure can only occur when
V
this high voltage, block contents are protected
against erasure. If block erase is attempted while
V
Successful
corresponding block lock-bit be cleared or, if set,
that RP# = V
the corresponding block lock-bit is set and
RP# = V
SR.5 will be set to “1.” Block erase operations with
V
should not be attempted.
4.6
Program is executed by a two-cycle command
sequence.
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the program and write verify algorithms
internally. After the program sequence is written,
the device automatically outputs status register
data when read (see Figure 8). The CPU can detect
the completion of the program event by analyzing
the RY/BY# pin or status register bit SR.7.
When program is complete, status register bit SR.4
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
successfully write to “0”s. The CUI remains in read
status register mode until it receives another
command.
Reliable programs only occurs when V
and V
voltage, memory contents are protected against
programs.
V
register bits SR.3 and SR.5 will be set to “1.”
18
CC
PP
IH
PP
< RP# < V
= V
PP
V
V
CC2/3
PPLK
IH
PPLK
Program Command
= V
, the block erase will fail, and SR.1 and
Program setup (standard 40H
If
, SR.3 and SR.5 will be set to “1.”
and V
, the operation will fail, and status
HH
PPH1/2/3
block
. If block erase is attempted when
HH
program
PP
produce spurious results and
. In the absence of this high
= V
erase
PPH1/2/3
is
requires
. In the absence of
attempted
CC
that
= V
while
CC2/3
the
or
Successful
corresponding block lock-bit be cleared or, if set,
that RP# = V
corresponding block lock-bit is set and RP# = V
program will fail, and SR.1 and SR.4 will be set to
“1.” Program operations with V
produce spurious results and should not be
attempted.
4.7
The Block Erase Suspend command allows
block-erase interruption to read or write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to
“1”).
Specification t
suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.8), a program operation
can also be suspended. During a program operation
with block erase suspended, status register bit
SR.7 will return to “0” and the RY/BY# output will
transition to V
indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V
Resume
automatically outputs status register data when
read (see Figure 9). V
(the same V
block erase is suspended. RP# must also remain at
V
erase). Block erase cannot resume until program
operations initiated during block erase suspend
have completed.
IH
or V
RY/BY#
HH
Block Erase Suspend
Command
command
(the same RP# level used for block
PP
program
HH
OL
WHRH2
. If program is attempted when the
. However, SR.6 will remain “1” to
level used for block erase) while
will
PP
also
defines the block erase
is
also
PRELIMINARY
must remain at V
written,
transition
OL
requires
. After the Erase
IH
< RP# < V
the
that
to
PPH1/2/3
device
V
the
OH
HH
IH
,
.