A1460A-3PQ208C MICROSEMI, A1460A-3PQ208C Datasheet - Page 18

• Manufacturer Part Number: A1460A-3PQ208C
• Manufacturer: MICROSEMI

Specifications of A1460A-3PQ208C

• Number Of Usable Gates: 6000
• Number Of Logic Blocks/elements: 848
• # Registers: 768
• # I/os (max): 167
• Frequency (max): 200MHz
• Process Technology: 0.8um (CMOS)
• Operating Supply Voltage (typ): 5V
• Logic Cells: 848
• Device System Gates: 15000
• Propagation Delay Time: 2ns
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Fixed Capacitance Values for Actel FPGAs
(pF)
Device Type
A1415A
A14V15A
A1425A
A14V25A
A1440A
A14V40A
A1440B
A1460A
A14V60A
A1460B
A14100A
A14V100A
A14100B
Fixed Clock Loads (s
Device Type
A1415A
A14V15A
A1425A
A14V25A
A1440A
A14V40A
A1440B
A1460A
A14V60A
A1460B
A14100A
A14V100A
A14100B
1-192
dedicated array
Clock Loads on
routed_Clk1
clock
105
100
105
165
157
165
195
185
195
104
160
160
288
288
288
432
432
432
697
697
697
1
104
60
57
75
72
s
r
/s
1
1
2
)
Clock Loads on
dedicated I/O
routed_Clk2
clock
165
157
165
195
185
195
140
168
168
168
228
228
228
105
100
105
100
100
140
140
60
57
75
72
80
80
r
s
2
2
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Logic Modules (m)
Inputs switching (n)
Outputs switching (p)
First routed array clock loads (q
Second routed array clock loads (q
Load capacitance (C
Average logic module switching rate
(f
Average input switching rate (f
Average output switching rate (f
Average first routed array clock rate
(f
Average second routed array clock rate
(f
Average dedicated array clock rate
(f
Average dedicated I/O clock rate (f
m
q1
q2
s1
)
)
)
)
L
)
n
)
1
p
)
)
2
s2
)
) = F
= 80% of modules
= # inputs/4
= # output/4
= 40% of
= 40% of
= 35 pF
= F/10
= F/5
= F/10
= F/2
= F/2
= F
sequential
modules
sequential
modules